More AMD "Strix Point" Mobile Processor Details Emerge

[btarunr]

"Strix Point" is the codename for AMD's next-generation mobile processor succeeding the current Ryzen 7040 series "Phoenix." More details of the processor emerged thanks to "All The Watts!!" on Twitter. The CPU of "Strix Point" will be heterogenous, in that it will feature two different kinds of CPU cores, but with essentially the same ISA and IPC. It is rumored that the processor will feature 4 "Zen 5" CPU cores, and 8 "Zen 5c" cores.

Both core types feature an identical IPC, but the "Zen 5" cores can hold onto higher boost frequencies, and have a wider frequency band, than the "Zen 5c" cores. From what we can deduce from the current "Zen 4c" cores, "Zen 5c" cores aren't strictly "efficiency" cores, as they still offer the full breadth of core ISA as "Zen 5," including SMT. In its maximum configuration, "Strix Point" will hence be a 12-core/24-thread processor. The two CPU core types sit in two different CCX (CPU core complexes), the "Zen 5" CCX has 4 cores sharing a 16 MB L3 cache, while the "Zen 5c" CCX shares a 16 MB L3 cache among 8 cores. AMD will probably use a software-based solution to ensure the right kind of workload from the OS is processed by the right kind of CPU core.



As for the integrated graphics, AMD is expected to deploy a large new iGPU based on the more advanced RDNA 3.5 graphics architecture, which has been referenced as "RDNA3+." It features 8 WGPs, or 16 CU, amounting to 1,024 stream processors, 64 TMUs, and an unknown number of ROPs (possibly 32), with the probable design goal of offering graphics performance close to a discrete Radeon RX 6500 XT graphics card. AMD will debut its second generation of the XDNA accelerator, the hardware backend of Ryzen AI. On "Strix Point," the accelerator is rumored to feature 64 AI Engines.

The chip's I/O is expected to be largely similar, with increase DDR5 memory speeds on offer—dual-channel (4x sub-channel) DDR5-5600 or LPDDR5X-8533, we don't know if AMD will update the PCIe interface to Gen 5 spec, the current "Phoenix" silicon is limited to Gen 4.

At this point, we don't know if "Strix Point" is a monolithic silicon, or a tiled processor, but AMD is expected to leverage the TSMC N4E (second gen 4 nm EUV) foundry node, for at least one of the tiles, or the whole die, in case this is a monolithic chip, with a total chip-area of around 225 mm².

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[TumbleGeorge]

current Ryzen 7045 series "Phoenix

Ryzen 7045 is "Dragon range".

 

[TheinsanegamerN]

A strix point with 16 CUs, 8533 mhz DDR5x, and a 3d cache would be SWEEET.

 

[hs4]

When power consumption is low enough and the clock is around 2 GHz, this configuration functions as 12 cores itself.

For an area equivalent to eight P cores, Intel's design, in which two of the P cores are replaced by E cores, has an MT performance equivalent to ten P cores. Strix Point, on the other hand, seems to have chosen to allocate four of the area of eight full cores to a reduced core to obtain MT performance equivalent to 12 cores.

 

[RamiHaidafy]

A Ryzen Z2 Extreme version of this should have a nice performance bump over the Z1 Extreme. Exciting times ahead.

 

[hs4]

A strix point with 16 CUs, 8533 mhz DDR5x, and a 3d cache would be SWEEET.

On the desktop packege, a V-Cache die of around 50 mm² is placed on a CCD of about 80 mm², and the excess 30 mm² is filled with dummy silicon (otherwise the die would be damaged from the corners).

The Phoenix Point is about 180mm², which is too much area for the V-Cache. To make mobile V-Cache, we need to do something we don't do now, such as removing all L3 from the main die and using a dedicated cache die for all L3 or L2. I don't think we will do all-V-Cache because it would mean abandoning everything except games.

 

[R0H1T]

What do you mean by abandon everything except

https://www.anandtech.com/show/2001...ew-ryzen-9-7945hx3d-with-3d-v-cache-impresses
https://www.notebookcheck.net/Asus-...e-world-s-fastest-gaming-laptop.742941.0.html

 

[hs4]

What do you mean by abandon everything except

https://www.anandtech.com/show/2001...ew-ryzen-9-7945hx3d-with-3d-v-cache-impresses
https://www.notebookcheck.net/Asus-...e-world-s-fastest-gaming-laptop.742941.0.html

If you like V-Cache, you need to know the difference between the monolithic Point series and the multi-die Range series.

 

[R0H1T]

Still not getting what you're trying to say? With x3d you're compromising on (general)application performance on laptops?

As for the physical implementation itself pretty sure AMD has probably half a dozen ways to skin the cat.

 

[hs4]

Still not getting what you're trying to say? With x3d you're compromising on (general)application performance on laptops?

As for the physical implementation itself pretty sure AMD has probably half a dozen ways to skin the cat.

It would simply increase costs and put them at a competitive disadvantage in price competition. Deterioration in heat dissipation characteristics is also a disadvantage in mobile, where heat dissipation devices are limited, albeit slightly.

 

[Yashyyyk]

V-Cache/X3D is way more efficient than the standard - super useful in laptops (1 sku lol) / SFF

 

[ixi]

If iGPU performance will be rx 6500xt then it is so cool. Next CPU for casual gaming .

 

[shoskunk]

TPU, Tom's, Anand, etc need to work on their sources.

C and non-C cores will be part of the same CCX. To do anything else with the available time-to-design and TSMC capabilities would place AMD further behind Intel for chips of this type.

AMD and partners would also be dealing with uneven distribution of heat across the package with c on one half and non-c on the other. That certaintly wouldnt work for desktop solutions.

I'll sit back and let this this post age like fine whine and you can see for yourself.

 

[DavidC1]

Strix Point, on the other hand, seems to have chosen to allocate four of the area of eight full cores to a reduced core to obtain MT performance equivalent to 12 cores.

Performance isn't going to be identical between 4 and 4c. The half area does come at a frequency cost, so it'll be lower in multi-threading. In reality it'll be closer to the "10 core" Intel.

 

[Wirko]

When power consumption is low enough and the clock is around 2 GHz, this configuration functions as 12 cores itself.

For an area equivalent to eight P cores, Intel's design, in which two of the P cores are replaced by E cores, has an MT performance equivalent to ten P cores. Strix Point, on the other hand, seems to have chosen to allocate four of the area of eight full cores to a reduced core to obtain MT performance equivalent to 12 cores.

AMD's Zen 4c cores are not half smaller than Zen 4, they are 30% or 35% smaller. But also Intel's E cores aren't 1/4 the size of P cores, they're closer to 1/3. Whose die space-saving technique will yield better results? Both will be very close, I think.

Of course AMD may also do something unexpected again with Zen 5, like packing 5c cores in clusters of two or four, and then the perf-power-area balance becomes less predictable.

 

[The Jniac]

So this is basically confirmation that Wendell from Level1Techs correctly predicted that AMD is going down the big.LITTLE route that Intel pioneered in the x86 market with Alder Lake and, in my opinion at least, doing it better. Come on AMD, give us a CPU with and 8-core Zen 5 X3D CCD and a 16-core Zen 5 c CCD.

I am also intrigued by the possibility (to clarify, this is something that I thought of; there is no reason to believe that AMD is planning on doing this) of having Zen C X3D CCDs, as the lower power, and thus heat output, of Zen C combined with the reduced L2 cache might pair nicely with 3D V-Cache.

 

[hs4]

AMD's Zen 4c cores are not half smaller than Zen 4, they are 30% or 35% smaller. But also Intel's E cores aren't 1/4 the size of P cores, they're closer to 1/3. Whose die space-saving technique will yield better results? Both will be very close, I think.

Of course AMD may also do something unexpected again with Zen 5, like packing 5c cores in clusters of two or four, and then the perf-power-area balance becomes less predictable.

I know exact difference in area. Using my own performance measurements and the measurements of Z1 by Chinese media to rigorously calculate efficiency, they are both similar around 2.0 GHz.

Gracemont vs Golden Cove
both at the same 2.0 GHz
MT perf./power: 1.0x
MT perf./area: 1.6x
ST perf.: 0.65x

both at their own maximum clock (3.8 GHz vs 5.2 GHz)
MT perf./power: 1.5x
MT perf./area: 1.2x
ST perf: 0.5x


Zen 4c vs Zen4
both at the same 2.0 GHz
MT perf./power: 1.0x
MT perf./area: 1.54x
ST perf.: 1.0x

both at own maximum clock (3.5 GHz vs 4.8 GHz)
MT perf./power: 1.0x
MT perf./area: 0.95x
ST perf: 0.75x