AMD "Zen 5c" CCDs Made On More Advanced 3 nm Node Than "Zen 5"

[btarunr]

AMD is reportedly building its upcoming "Zen 5" and "Zen 5c" CPU Core Dies (CCDs) on two different foundry nodes, a report by Chinese publication UDN, claims. The Zen 5 CCD powering the upcoming Ryzen "Granite Ridge" desktop processors, "Fire Range" mobile processors, and EPYC "Turin" server processors, will be reportedly built on the 4 nm EUV foundry node, a slightly more advanced node than the current 5 nm EUV the company is building "Zen 4" CCDs on. The "Zen 5c" CCD, or the chiplet with purely "Zen 5c" cores in a high density configuration; on the other hand, will be built on an even more advanced 3 nm EUV foundry node, the report says. Both CCDs will go into mass production in Q2-2024, with product launches expected across the second half of the year.

The "Zen 5c" chiplet has a mammoth 32 cores spread across two CCXs of 16 cores, each. Each CCX has 16 cores sharing a 32 MB L3 cache. It is to cram these 32 cores, each with 1 MB of L2 cache; and a total of 64 MB of L3 cache, that AMD could be turning to the 3 nm foundry node. Another reason could be voltages. If "Zen 4c" is anything to go by, the "Zen 5c" core is a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets. The decision to go with 3 nm could be a move aimed at increasing clock speeds at those lower voltages, in a bid to generationally improve performance using clock speeds, besides IPC and core count. The EPYC processor with "Zen 5c" chiplets will feature no more than six such large CCDs, for a maximum core count of 192. The regular "Zen 5" CCD has just 8 cores in a single CCX, with 32 MB of L3 cache shared among the cores; and TSV provision for 3D Vertical Cache, to increase the L3 cache in special variants.



View at TechPowerUp Main Site | Source

 

[Fishymachine]

Might also have to do with the fact that it's easier to fab smaller, simpler chips on bleeding edge nodes, or that N3(P) is more mobile/low power optimized

 

[Daven]

My dream Ryzen 9 9950X3D could become a reality.

Eight Zen 5 cores, 4 nm, 6.0+ GHz
16 Zen 5c cores, 3 nm, 128 MB 3D cache

All in one package for a total of 24 cores / 48 threads and up to 15% generational IPC uplift across all cores.

 

[Count von Schwalbe]

Might also have to do with the fact that it's easier to fab smaller, simpler chips on bleeding edge nodes, or that N3(P) is more mobile/low power optimized

I am pretty sure the chip is larger, as it has a bunch more cores.

 

[R0H1T]

Strix Halo/point looking even more exciting now!

 

[Denver]

I am pretty sure the chip is larger, as it has a bunch more cores.

But the Zen5c cores are smaller, and the L3 cache is what takes up the most space on the die, in this case it's just 1MB/core vs 4Mb/core on the regular Zen5.

16-core "Zen 4c" CCD just 9.6% larger in die-area, than the 8-core "Zen 4" CCD. That's 72.7 mm² per CCD, compared to 66.3 mm² of the regular 8-core "Zen 4" CCD.

 

[Robin Seina]

This actually makes sense. Zen5c cores will be smaller (no circuits for high frequencies and better node) and have lower frequencies, so they can use node created for smartphone chips which offers better energy efficiency but has lower frequencies.

 

[Count von Schwalbe]

But the Zen5c cores are smaller, and the L3 cache is what takes up the most space on the die, in this case it's just 1MB/core vs 4Mb/core on the regular Zen5.

16-core "Zen 4c" CCD just 9.6% larger in die-area, than the 8-core "Zen 4" CCD. That's 72.7 mm² per CCD, compared to 66.3 mm² of the regular 8-core "Zen 4" CCD.

Indeed, but now there are 32 cores. So the chip will be significantly larger, even though each core is significantly smaller. I would be interested in the yield rate on this one.

 

[Daven]

Why would an Epyc processor with Zen 5c have only six chiplets? That’s an odd arrangement. Wouldn’t eight chiplets for a total of 256 cores make more sense? That’s how Bergamo is arranged.

 

[Tek-Check]

Well, we had heard this from Tom from MLID last year already, namely that Zen5 c cores will be on 3nm. He had a good leak for this one.

My dream Ryzen 9 9950X3D could become a reality.

Eight Zen 5 cores, 4 nm, 6.0+ GHz
16 Zen 5c cores, 3 nm, 128 MB 3D cache

All in one package for a total of 24 cores / 48 threads and up to 15% generational IPC uplift across all cores.

It's not going to happen. Not enough space on current design of the package.

 

[Daven]

Well, we had heard this from Tom from MLID last year already, namely that Zen5 c cores will be on 3nm. He had a good leak for this one.


It's not going to happen. Not enough space on current design of the package.

I’m wishing for a 16 core Zen 5c chiplet on desktop not the 32 core server version. As someone pointed out, Zen 4c 16 core is only 10% bigger than Zen 4 eight core. If this is the case with Zen 5 eight core and Zen 5c 16 core then there’s plenty of room.

 

[Panther_Seraphin]

My dream Ryzen 9 9950X3D could become a reality.

Eight Zen 5 cores, 4 nm, 6.0+ GHz
16 Zen 5c cores, 3 nm, 128 MB 3D cache

All in one package for a total of 24 cores / 48 threads and up to 15% generational IPC uplift across all cores.

You wont get X3D on the c variants due to the fact that they min/max usable space for cores so the areas where the vias would be to house the X3D are not included.

So would most likely end up with the Zen 5 COre with X3D and the C ones without. It may be a way of keeping all the frequencys on the die the same however.

 

[dgianstefani]

I'm guessing it's simply easier to get production budgets if you allocate on two or multiple different nodes.

Intel is already doing this.

 

[Nhonho]

It would be nice if the news here had a little more technical details. The followers here are nerds, you know it..

Do you know how many nanometers the transistors for the cache memories of TSMC's 4 and 3 nm nodes are made of?

My dream Ryzen 9 9950X3D could become a reality.

Eight Zen 5 cores, 4 nm, 6.0+ GHz
16 Zen 5c cores, 3 nm, 128 MB 3D cache

All in one package for a total of 24 cores / 48 threads and up to 15% generational IPC uplift across all cores.

Do you use any app that uses this many cores? If so, what are they?

Nowadays, practically all operations that were/are too heavy for CPUs are done quickly by GPUs, such as rendering and encoding videos.

 

[Knight47]

Can't wait for the 9000X3D with the rumored 20% single and +40% IPC in multi-core performance that should come in May 2024

 

[dgianstefani]

Can't wait for the 9000X3D with the rumored 20% single and +40% IPC in multi-core performance that should come in May 2024

Where did you get may from?

X3D chips usually release a good while after the standard architecture.

 

[Robin Seina]

Where did you get may from?

X3D chips usually release a good while after the standard architecture.

Yes, Zen 5 looks like release on Computex 2024, while Zen 5 X3D usually comes with some delay, so probably a CES 2025...

 

[Knight47]

Where did you get may from?

X3D chips usually release a good while after the standard architecture.

I've read on X and reddit that Zen5 comes in April since it's in mass production and 3D might launch right away or close to the initial launch.

 

[Onasi]

I've read on X and reddit that Zen5 comes in April since it's in mass production and 3D might launch right away or close to the initial launch.

Unlikely. AMD will need some time to ramp up the production in order to reliably get chips that would be suitable for X3D applications. I would be very surprised if the release delay for those would be less than 6 months.

 

[Haku]

My dream Ryzen 9 9950X3D could become a reality.

Eight Zen 5 cores, 4 nm, 6.0+ GHz
16 Zen 5c cores, 3 nm, 128 MB 3D cache

All in one package for a total of 24 cores / 48 threads and up to 15% generational IPC uplift across all cores.

I don't think AMD will go with Zen5c Cores for their high end offers, but it's doesn't sound like a dream, it's quite reachable if AMD want to do so

 

[dgianstefani]

I don't think AMD will go with Zen5c Cores for their high end offers, but it's doesn't sound like a dream, it's quite reachable if AMD want to do so

R9 8900 would be good for a change if it was, say, 8 Zen 5 + 8 Zen 5C, instead of this 6+6 questionable chip it is today.

R9 8950 being 8+8 full Zen 5 as a change, with higher clocks.

 

[kapone32]

R9 8900 would be good for a change if it was, say, 8 Zen 5 + 8 Zen 5C, instead of this 6+6 questionable chip it is today.

R9 8950 being 8+8 full Zen 5 as a change, with higher clocks.

Since when are chips like the 5900X questionable?

 

[Metroid]

This means 16 cores x3d possible in one chiplet just like 7800x3d. If this is indeed true, that means one zen5 ccd will be 16 cores, on 7800x3d one ccd is 8 cores. So maybe 9800x3d will be a 16 cores, 32 threads smt enabled, one ccd.

R9 8900 would be good for a change if it was, say, 8 Zen 5 + 8 Zen 5C, instead of this 6+6 questionable chip it is today.

R9 8950 being 8+8 full Zen 5 as a change, with higher clocks.

It's a fact that AMD has been skipping one series number xxxx regarding zen gen cpus, so it has a great chance to be 9xxx series.

Where did you get may from?

X3D chips usually release a good while after the standard architecture.

There is evidence the x3d cpus will come together with the non x3d ones this time around.

 

[Tek-Check]

I’m wishing for a 16 core Zen 5c chiplet on desktop not the 32 core server version. As someone pointed out, Zen 4c 16 core is only 10% bigger than Zen 4 eight core. If this is the case with Zen 5 eight core and Zen 5c 16 core then there’s plenty of room.

Perhaps. It is not clear whether AMD is ready to scale hybrid design on CCD level. We only have small hybrid monolithic design Phoenix 2.

 

[dgianstefani]

This means 16 cores x3d possible in one chiplet just like 7800x3d. If this is indeed true, that means one zen5 ccd will be 16 cores, on 7800x3d one ccd is 8 cores. So maybe 9800x3d will be a 16 cores, 32 threads smt enabled, one ccd.

No, it doesn't.

Zen xC doesn't have the ability to have 3DVCache.