AMD EPYC "Venice" Leak: 2 nm Zen 6 and Zen 6c to Offer Up to 256C/512T and 1 GB of L3 in a Single Socket

[AleksandarK]

AMD is preparing to set a new data-center performance bar with its upcoming 6th-generation EPYC "Venice" processors, built on the latest "Zen 6" and "Zen 6C" core designs and the industry's first 2 nm-class node from TSMC. Leaked engineering diagrams and forum reports suggest Venice will offer additional core scalability, memory capacity, and cache productivity for demanding server workloads. At the heart of the Venice platform lies a multi-chip module design featuring up to eight Core Complex Dies (CCDs) arrayed around one or more central I/O dies (IODs). In its Zen 6 configuration, each CCD houses 12 "classic" cores, yielding a maximum of 96 cores and 192 threads per socket. The cache per CCD is rumored to reach 128 MB of shared L3, double that of its predecessor, delivering up to 1 TB of L3 cache in a fully populated eight-CCD package.

For customers prioritizing raw thread count over per-core performance, the Zen 6C variant pushes the envelope to 256 "dense" cores and 512 threads by leveraging a leaner core design and higher CCD count. Despite the density boost, each Zen 6C core maintains 2 MB of L3 cache, preserving latency benefits even at scale. Memory bandwidth also receives a major uplift: Venice will support both 16-channel (SP7) and 12-channel (SP8) DDR5 configurations, accommodating up to 6 TB of system RAM per socket. The number of PCIe Gen 5 lanes is still unknown, but it could be well over 128 lanes, which the past 5th-generation EPYC CPUs had. Thermal and power targets differentiate the two sockets: SP7 models are expected to reach TDPs around 600 W, up from 400 W on current Zen 5 chips, while SP8 parts aim for 350-400 W to suit more moderate-density racks. This tiered approach will let hyperscalers and enterprise customers balance performance, efficiency, and cooling infrastructure, especially at the scale that hyperscalers have. A projected launch date is scheduled for late 2025 or early 2026.



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[Chaitanya]

Thats a lot of cores and licensing is going to be a headache to manage with that kind of CPU core count on single socket.

 

[RandallFlagg]

Not sure who checks these rumors, but I find it super unlikely that we'll see an TSMC N2 AMD product in 2025.

TSMC is not even planning to do volume until maybe late Q4. And that's probably going to be ramp for Apple, not AMD. And even if it were AMD getting first dibs, you wouldn't see the chips until 2026.

Tom's has a more realistic release of H2 2026, but I find even that to be overly optimistic. More likely Q4 2026 / Q1 2027, after Apple gets the bulk of its N2 allotment.

 

[Bruno Vieira]

12c per CCD means 10950x with 24c/48 t, a nice upgrade for the final AM5 part. It's a shame it's limited to only dual channels, but it gives me hope for Strix Halo 2.

 

[RandallFlagg]

Thats a lot of cores and licensing is going to be a headache to manage with that kind of CPU core count on single socket.

The big numbers sound good in press releases, but I don't think I've actually encountered a system using more than 64 cores in a socket. Software licenses cost a *lot* more than CPUs, so generally you want more powerful cores. Probably 128+ cores are useful for cloud providers like Amazon, Google, Microsoft, IBM and not so much everyone else.

 

[Chaitanya]

12c per CCD means 10950x with 24c/48 t, a nice upgrade for the final AM5 part. It's a shame it's limited to only dual channels, but it gives me hope for Strix Halo 2.

if it gets new IO die with support for clocked UDIMMs and DDR5 sub channels then things could certainly improve. I really hope final AM5 CPUs are able to support 256GB of RAM without any issues unlike current ones which struggle with all 4 slots occupied and with capacities above 64GBs.

 

[JustBenching]

12c per CCD means 10950x with 24c/48 t, a nice upgrade for the final AM5 part. It's a shame it's limited to only dual channels, but it gives me hope for Strix Halo 2.

And 12c for the 10800x. That's good, finally they moved out of 6 and 8 core parts for the midrange.

 

[Bruno Vieira]

if it gets new IO die with support for clocked UDIMMs and DDR5 sub channels then things could certainly improve. I really hope final AM5 CPUs are able to support 256GB of RAM without any issues unlike current ones which struggle with all 4 slots occupied and with capacities above 64GBs.

I used a 7950x with 96gb @ 6000 CL28 for a year, it was a mini-ITX MSI B650 Edge, but stable anyway. There are 64gb sticks on the market, but none is high-perf so far. Memory BW is the reason I am moving to Strix Halo, and without the cost/weight of a TR.

 

[JustBenching]

I used a 7950x with 96gb @ 6000 CL28 for a year, it was a mini-ITX MSI B650 Edge, but stable anyway. There are 64gb sticks on the market, but none is high-perf so far. Memory BW is the reason I am moving to Strix Halo, and without the cost/weight of a TR.

96gb @ 7200 work on a 285k, around 120gb of read / write with stock xmp.

 

[freeagent]

They brought Venice back

Regardless of the name, I am excited

 

[111frodon]

"delivering up to 1 TB of L3 cache"

I think this should say 1 GB instead of 1 TB...

 

[bug]

The big numbers sound good in press releases, but I don't think I've actually encountered a system using more than 64 cores in a socket. Software licenses cost a *lot* more than CPUs, so generally you want more powerful cores. Probably 128+ cores are useful for cloud providers like Amazon, Google, Microsoft, IBM and not so much everyone else.

Doesn't matter you have encountered or not, servers can always put this to good use, whether in the cloud or on-prem.
The project I'm currently working on made the mistake of putting the build machine in the cloud. Lost a lot of $$$ because of that, the machine is always on and will chew through 30+ for a single build. Get one of these on-prem, run 4 builds at the same time with a few cores to spare...

 

[Wirko]

if it gets new IO die with support for clocked UDIMMs and DDR5 sub channels then things could certainly improve. I really hope final AM5 CPUs are able to support 256GB of RAM without any issues unlike current ones which struggle with all 4 slots occupied and with capacities above 64GBs.

Are subchannels not supported on any known DDR5 platform?

 

[Chaitanya]

Are subchannels not supported on any known DDR5 platform?

Intel Core 200 series supports it so far.

 

[A Computer Guy]

12c per CCD means 10950x with 24c/48 t, a nice upgrade for the final AM5 part. It's a shame it's limited to only dual channels, but it gives me hope for Strix Halo 2.

And limited by PCIe lanes. My Threadripper and I are crying right now - but for different reasons.

 

[petr88]

256 Cores at 6GHZ?

 

[A Computer Guy]

Doesn't matter you have encountered or not, servers can always put this to good use, whether in the cloud or on-prem.
The project I'm currently working on made the mistake of putting the build machine in the cloud. Lost a lot of $$$ because of that, the machine is always on and will chew through 30+ for a single build. Get one of these on-prem, run 4 builds at the same time with a few cores to spare...

Was it Amazon by any chance stripping away $$$ for every I/O?

 

[Vayra86]

They brought Venice back

Regardless of the name, I am excited

Kinda want to buy one, put it under water and call the rig Atlantis.

 

[Tek-Check]

Not sure who checks these rumors, but I find it super unlikely that we'll see an TSMC N2 AMD product in 2025.

There are no rumors about Zen6 in 2025. It's all about 2026.

 

[RandallFlagg]

There are no rumors about Zen6 in 2025. It's all about 2026.

The last sentence in the OP post in this thread says, regarding the Zen 6c, and I quote :

"A projected launch date is scheduled for late 2025 or early 2026."

 

[Tek-Check]

The last sentence in the OP post in this thread says, regarding the Zen 6c,

I know, but there is no indication that this would actually happen.

 

[OkieDan]

12c per CCD means 10950x with 24c/48 t, a nice upgrade for the final AM5 part. It's a shame it's limited to only dual channels, but it gives me hope for Strix Halo 2.

The next gen in the 5950x/7950x/9950x series would be 11950x wouldn't it?

Hopefully intel comes upwith something competitive to keep AMD pricing sane.

 

[Caring1]

"delivering up to 1 TB of L3 cache"

I think this should say 1 GB instead of 1 TB...

It won't happen overnight, but it will happen.

 

[beautyless]

The next gen in the 5950x/7950x/9950x series would be 11950x wouldn't it?

They named every Zen 5 mobile APU "Ryzen AI 300."
If the desktop APU parts are the same, it's possible they'll use the 10000 series when it becomes available.
Then, Zen 6 CPUs would be called "Ryzen 11000," and Zen 6 APUs would be "Ryzen AI 400," marking the final Ryzen lineup.
Oh, I really dislike the Radeon 90X0 naming scheme for inconsistency reason.

 

[user556]

They named every Zen 5 mobile APU "Ryzen AI 300."
If the desktop APU parts are the same, ...

This article is about the leading edge CPU chiplet CCDs, used in SPx and AMx sockets. Not the later arriving APUs.

I suspect each Zen6C CCD will be two CCX of 16 cores and 64 MB L3 cache. That's how you end up with total of 32 cores and 128 MB L3. And the 6C CCD is physically much longer than other CCDs, so only one can fit in the AM5 socket form.