Monday, May 12th 2025
AMD EPYC "Venice" Leak: 2 nm Zen 6 and Zen 6c to Offer Up to 256C/512T and 1 GB of L3 in a Single Socket
AMD is preparing to set a new data-center performance bar with its upcoming 6th-generation EPYC "Venice" processors, built on the latest "Zen 6" and "Zen 6C" core designs and the industry's first 2 nm-class node from TSMC. Leaked engineering diagrams and forum reports suggest Venice will offer additional core scalability, memory capacity, and cache productivity for demanding server workloads. At the heart of the Venice platform lies a multi-chip module design featuring up to eight Core Complex Dies (CCDs) arrayed around one or more central I/O dies (IODs). In its Zen 6 configuration, each CCD houses 12 "classic" cores, yielding a maximum of 96 cores and 192 threads per socket. The cache per CCD is rumored to reach 128 MB of shared L3, double that of its predecessor, delivering up to 1 TB of L3 cache in a fully populated eight-CCD package.
For customers prioritizing raw thread count over per-core performance, the Zen 6C variant pushes the envelope to 256 "dense" cores and 512 threads by leveraging a leaner core design and higher CCD count. Despite the density boost, each Zen 6C core maintains 2 MB of L3 cache, preserving latency benefits even at scale. Memory bandwidth also receives a major uplift: Venice will support both 16-channel (SP7) and 12-channel (SP8) DDR5 configurations, accommodating up to 6 TB of system RAM per socket. The number of PCIe Gen 5 lanes is still unknown, but it could be well over 128 lanes, which the past 5th-generation EPYC CPUs had. Thermal and power targets differentiate the two sockets: SP7 models are expected to reach TDPs around 600 W, up from 400 W on current Zen 5 chips, while SP8 parts aim for 350-400 W to suit more moderate-density racks. This tiered approach will let hyperscalers and enterprise customers balance performance, efficiency, and cooling infrastructure, especially at the scale that hyperscalers have. A projected launch date is scheduled for late 2025 or early 2026.
Sources:
@Squash, Wccftech
For customers prioritizing raw thread count over per-core performance, the Zen 6C variant pushes the envelope to 256 "dense" cores and 512 threads by leveraging a leaner core design and higher CCD count. Despite the density boost, each Zen 6C core maintains 2 MB of L3 cache, preserving latency benefits even at scale. Memory bandwidth also receives a major uplift: Venice will support both 16-channel (SP7) and 12-channel (SP8) DDR5 configurations, accommodating up to 6 TB of system RAM per socket. The number of PCIe Gen 5 lanes is still unknown, but it could be well over 128 lanes, which the past 5th-generation EPYC CPUs had. Thermal and power targets differentiate the two sockets: SP7 models are expected to reach TDPs around 600 W, up from 400 W on current Zen 5 chips, while SP8 parts aim for 350-400 W to suit more moderate-density racks. This tiered approach will let hyperscalers and enterprise customers balance performance, efficiency, and cooling infrastructure, especially at the scale that hyperscalers have. A projected launch date is scheduled for late 2025 or early 2026.
24 Comments on AMD EPYC "Venice" Leak: 2 nm Zen 6 and Zen 6c to Offer Up to 256C/512T and 1 GB of L3 in a Single Socket
TSMC is not even planning to do volume until maybe late Q4. And that's probably going to be ramp for Apple, not AMD. And even if it were AMD getting first dibs, you wouldn't see the chips until 2026.
Tom's has a more realistic release of H2 2026, but I find even that to be overly optimistic. More likely Q4 2026 / Q1 2027, after Apple gets the bulk of its N2 allotment.
Regardless of the name, I am excited :)
I think this should say 1 GB instead of 1 TB...
The project I'm currently working on made the mistake of putting the build machine in the cloud. Lost a lot of $$$ because of that, the machine is always on and will chew through 30+ for a single build. Get one of these on-prem, run 4 builds at the same time with a few cores to spare...
"A projected launch date is scheduled for late 2025 or early 2026."
Hopefully intel comes upwith something competitive to keep AMD pricing sane.
If the desktop APU parts are the same, it's possible they'll use the 10000 series when it becomes available.
Then, Zen 6 CPUs would be called "Ryzen 11000," and Zen 6 APUs would be "Ryzen AI 400," marking the final Ryzen lineup.
Oh, I really dislike the Radeon 90X0 naming scheme for inconsistency reason.
I suspect each Zen6C CCD will be two CCX of 16 cores and 64 MB L3 cache. That's how you end up with total of 32 cores and 128 MB L3. And the 6C CCD is physically much longer than other CCDs, so only one can fit in the AM5 socket form.