AMD Readies "Gorgon Point" Mobile Processor for 2026: Zen 5 + RDNA 3.5

[btarunr]

AMD presented its next generation mobile processor that succeeds its current Ryzen AI 300 "Strix Point" to its industry partners. This presentation allegedly got leaked to the web. The 2026 successor to "Strix Point" is codenamed "Gorgon Point," and offers a significant single-threaded performance uplift while interestingly retaining the CPU core and iGPU IP. The slides mention "Gorgon Point" as combining up to 12 CPU cores based on "Zen 5" or "Zen 5c," an iGPU based on the RDNA 3.5 graphics architecture, and an NPU based on XDNA 2—so for the most part the IP is unchanged. The CPU, iGPU, and NPU, get performance upgrades over the current "Strix Point" chip.

AMD accompanied the specs slides with first party performance numbers. The multithreaded CPU performance numbers are moderately higher, which seem to indicate that the CPU core configuration of 4x "Zen 5" + 8x "Zen 5c" seems to be carried over; but the single-threaded performance sees a significant increase. We're not sure what's driving this, but there are two theories. The more obvious one is a significant increase in clock speeds, helped by an updated power management; but the second more radical theory is that AMD updated the "Zen 5" P-cores to have full fat 512-bit FP capabilities, similar to the "Zen 5" cores in "Fire Range" and "Strix Halo" processors. If you recall, the "Zen 5" cores in "Strix Point" have their FPUs limited to dual-pumped 256-bit paths to execute AVX512 instructions, a design choice probably driven by power considerations. The NPU throughput has been moderately increased to deliver over 55 AI TOPS, AMD enabled the full NPU performance across all tiers of Ryzen AI SKUs based on this chip. In all, "Gorgon Point" is to "Strix Point" what "Hawk Point" was to "Phoenix Point."



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[10tothemin9volts]

I was thinking, why no RDNA 4 again, then I saw:

[..] In all, "Gorgon Point" is to "Strix Point" what "Hawk Point" was to "Phoenix Point."

@btarunr Thanks for adding this. I see, so it's the same/refresh chip (because it's the same process node, which is the underlying basis for everything when it comes to chips basically) with a slight overclock. Not every generation is a new APU/chip/process node, aka, same may call it the tick-tock model (a new chip every 2nd generation). Let's hope TSMC keeps continue advancing so that AMD won't be forced to switch to a tick-tock-toe cadence (a new chip every 3rd generation).

 

[ymdhis]

Ready some new APUs for AM5 already.

 

[ModEl4]

@btarunr Where did you see significant single-threaded performance uplift?

 

[FiRe]

What's RNDA?

 

[TristanX]

Look like Zen6 cores only for Server and desktop as CCD

 

[AKBrian]

@btarunr Where did you see significant single-threaded performance uplift?

Yeah, I think they're severely misinterpreting the (admittedly, deep fried) graphs. The uplift appears to be in the 4-12% range for both 1T and nT, with the larger gains being nT at higher wattage.

 

[john_]

All welcome to the era where the refresh is mostly justified by the upgraded NPU unit.

 

[Baba]

We're not sure what's driving this, but there are two theories. The more obvious one is a significant increase in clock speeds

No need for theories.

 

[NoLoihi]

I see, so it's the same/refresh chip (because it's the same process node, which is the underlying basis for everything when it comes to chips basically) with a slight overclock. Not every generation is a new APU/chip/process node, aka, same may call it the tick-tock model (a new chip every 2nd generation). Let's hope TSMC keeps continue advancing so that AMD won't be forced to switch to a tick-tock-toe cadence (a new chip every 3rd generation).

Neither is true: Tocks were the significant progress steps of Intel’s development, where architecture changed, but node stayed mostly the same (with maybe small improvements). Ticks, however, were node changes with mostly minor architectural adjustments.
What we’ll be getting with Gorgon Point is a plain refresh, as we’ve seen many before. Same as 14th gen. Core over 13th gen, for instance.

If you recall, the "Zen 5" cores in "Strix Point" have their FPUs limited to dual-pumped 256-bit paths to execute AVX512 instructions, a design choice probably driven by power considerations.

I must have missed that, I feel like AMD’s really keeping people on their toes with such a choice for product segmentation (still calling all of them Zen 5)! … I would have taken Halo’s FP throughput as indicative of Point’s, no question, so one would have to wonder how many others would’ve been misled that way as well …

 

[Chet_Manly]

I was thinking, why no RDNA 4 again, then I saw:

@btarunr Thanks for adding this. I see, so it's the same/refresh chip (because it's the same process node, which is the underlying basis for everything when it comes to chips basically) with a slight overclock. Not every generation is a new APU/chip/process node, aka, same may call it the tick-tock model (a new chip every 2nd generation). Let's hope TSMC keeps continue advancing so that AMD won't be forced to switch to a tick-tock-toe cadence (a new chip every 3rd generation).

FS4 would be such a massive improvement too. Shame.

 

[bitsandboots]

These names are getting out of control... but it's a cool one at least.

 

[stickleback123]

LOL at AMD sticking "AI" into all it's product names to jump on the bandwagon, echoes of "Athlon XP" to try and ride the coat tails of Windows XP.

I worked with marketing weasels and the conceit of them calling themselves "creative" when they're all bandwagon hopping sheep was real

 

[Fasola]

echoes of "Athlon XP" to try and ride the coat tails of Windows XP.

Quite the nugget of trivia. I've never associated the two or heard anyone else for that matter.

 

[medi01]

9070 shows record perf/watt this gen, but we have 0 gaming laptops with AMD dGPUs.

And there is only a handful of overpriced "AI" laptops with AMD APUs with overpowered GPUs...

 

[Mr_Engineer]

It's most likely these Gordon Point APUs will be built on TSMC 3nm process, which would allow a considerable die size and power draw reduction, while also allowing higher clocks, and possibly a larger L3 cache.