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AMD Ryzen 9000X3D Processors with 3D V-Cache Arrive in January at CES 2025

Wirko said:
Yes, the arrangement seems weird. I think the IOD needs to be placed close to the centre because all signals from the LGA (the land grid array) are connected to it, and that's part of the issue. But I don't understand why the CCDs had to be moved that far to the edge of the package. Too many wires in between? How many wires does each IF link take?
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It's a complex topic, so to think you have any insight (not trying to be rude) is just a little naive. Read THIS in its entirety and you'll only have a small grasp of WHY the layouts are done as they are. Signal integrity, engineering limits etc.

AMD Technical Information Portal

docs.amd.com docs.amd.com
 
photonboy said:
It's a complex topic, so to think you have any insight (not trying to be rude) is just a little naive. Read THIS in its entirety and you'll only have a small grasp of WHY the layouts are done as they are. Signal integrity, engineering limits etc.

AMD Technical Information Portal

docs.amd.com docs.amd.com
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For sure tracing multilayered PCBs is not trivial. From trace lengths to equal lengths... tracing angles and I'm sure many more.
Its not that they have too many degrees of freedom, quite the contrary.
 
I might buy Arrow Lake then. Was hoping for a 9000X3D vs Arrow Lake clash in Q4.
 
photonboy said:
It's a complex topic, so to think you have any insight (not trying to be rude) is just a little naive. Read THIS in its entirety and you'll only have a small grasp of WHY the layouts are done as they are. Signal integrity, engineering limits etc.

AMD Technical Information Portal

docs.amd.com docs.amd.com
Click to expand...
Of course there are many considerations that I can't think of (and several that I can think of). Current density for power delivery is limited, and signal wire density is limited too, and also what @Zach_01 said, plus crosstalk and interferences, and more.

The gap between the IOD and CCDs is surprisingly large but the IFOP link is wide too. 128 bits per direction per link, or is it more? Diagrams like this one (Zen 3) do show, in part, why there's such a gap. That gap is significantly smaller in Epycs (but we don't know the number of layers on substrate).

Also in Zen 4, AMD moved the IOD closer to the centre, and the CCDs closer to the edge, by 1.6 mm (as measured by der8auer). That's weird.

Another hard to explain design decision is the orientation. The CCDs are the closest to the PCIe slots and away from the VRMs, even though they consume most of the power. The IOD is closest to the VRMs and away from the PCIe slots, even though all PCIe and other signals run from it. My naive EE mind tends to think that this causes many problems with space constraints and interference because too many power and signal wires have to run over each other on the substrate.
 
Regarding 3DVcache implementation...

Steeve from GN said that Woligroski is not making things up, and that has information from unofficial channels that some key changes are at place.

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Zach_01 said:
Regarding 9000X3D implementation...

Steeve from GN said that Woligroski is not making things up, and that has information from unofficial channels that some key changes are at place.

View attachment 361167
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One thing I can think of is an extension of L2 in addition to L3. If it adds four cycles of latency like it does in Zen 3 and 4, it won't be exactly great, but maybe still worth the effort.
 
Zach_01 said:
Regarding 3DVcache implementation...

Steeve from GN said that Woligroski is not making things up, and that has information from unofficial channels that some key changes are at place.

View attachment 361167
Click to expand...
Cool. Worst-case scenario it's basically no worse and it'll mean 7800X3D pricing should start to drop as there'll be no real reason to buy one for the same price as a 9800X3D.

If the vague hints are more than just optimism then everyone wins. Well, everyone except Intel.
 
Zach_01 said:
. since Zen5 showed that its more bandwidth and latency sensitive (look reviews with tweaked memory)... even the exactly the same cache as the 7000X3Ds have, it will probably be benefited more.
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It cost everybody 0zero€$ to recommend ddr5 6000 or 6400 cl30/28 and sell expo cl30 or cl28. Problem is at least 1 main reviewer had trobles running 6000 cl30. Long boot times also tanked. They have to do something with that IMC / Infinity Fabric even goes up to zen6 for changes. These and agesa and asmedia hold amd back imho. I’m not an engineering, but I think they could sell 8cores with larger L1 and L2 caches to justify upgrades. We ll see if avx512 is needed on gaming cpus
 
cerulliber said:
It cost everybody 0zero€$ to recommend ddr5 6000 or 6400 cl30/28 and sell expo cl30 or cl28. Problem is at least 1 main reviewer had trobles running 6000 cl30. Long boot times also tanked. They have to do something with that IMC / Infinity Fabric even goes up to zen6 for changes. These and agesa and asmedia hold amd back imho. I’m not an engineering, but I think they could sell 8cores with larger L1 and L2 caches to justify upgrades. We ll see if avx512 is needed on gaming cpus
Click to expand...
I found Reddit link so this might be true.
 
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