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AMD Unveils "Zen 2" CPU Architecture and 7 nm Vega Radeon Instinct MI60 at New Horizon

btarunr

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AMD today held its "New Horizon" event for investors, offering guidance and "color" on what the company's near-future could look like. At the event, the company formally launched its Radeon Instinct MI60 GPU-based compute accelerator; and disclosed a few interesting tidbits on its next-generation "Zen 2" mircroarchitecture. The Instinct MI60 is the world's first GPU built on the 7 nanometer silicon fabrication process, and among the first commercially available products built on 7 nm. "Rome" is on track to becoming the first 7 nm processor, and is based on the Zen 2 architecture.

The Radeon Instinct MI60 is based on a 7 nm rendition of the "Vega" architecture. It is not an optical shrink of "Vega 10," and could have more number-crunching machinery, and an HBM2 memory interface that's twice as wide that can hold double the memory. It also features on-die logic that gives it hardware virtualization, which could be a boon for cloud-computing providers.



If you've been paying attention to our "Zen 2" coverage over the past couple of weeks, you would've read our recent article citing a Singapore-based VLSI engineer claiming that AMD could disintegrate the northbridge for its high core-count enterprise CPUs, in an attempt to make the memory I/O "truly" wide, without compromising on the idea of MCM CPU chiplets. All of that is true.

"Rome" is codename for a multi-chip module of four to eight 7 nm CPU dies, wired to a centralized die over InfinityFabric. This 14 nm die, called "I/O die," handles memory and PCIe, providing a monolithic 8-channel memory interface, overcoming the memory bandwidth bottlenecks of current-generation 4-die MCMs. The CPU dies and an I/O die probably share an interposer. Assuming each die has 8 CPU cores, "Rome" could have up to 64 cores, an 8-channel DDR4 memory interface, and a 96-lane PCI-Express gen 4.0 root-complex, per socket. If AMD has increased its core-count per CPU die, Rome's core count could be even higher.



The broader memory I/O, assuming InfinityFabric does its job, could significantly improve performance of multi-threaded workloads that can scale across as many cores as you can throw at them, utilizing a truly broader memory interface. AMD also speaks of "increased IPC," which bodes well for the client-segment. AMD has managed to increase IPC (per-core performance), with several on-die enhancements to the core design.

With "Zen" and "Zen+," AMD recognized several components on the core that could be broadened or made faster, which could bring about tangible IPC improvements. This includes a significantly redesigned front-end. Zen/Zen+ feature a front-end that's not much different than AMD's past micro-architectures. The new front-end includes an improved branch-predictor, a faster instruction prefetcher, an improved/enlarged L1 instruction cache, and an improved prefetcher cache (L2).

The number-crunching machinery, the floating point unit, also receives a massive overhaul. "Zen 2" features 256-bit FPUs, which are doubled in width compared to Zen. load/store/dispatch/retire bandwidths have been doubled over the current generation. These changes are massive. Given that even without these core-level changes, by simply improving cache latencies, AMD managed to eke out a ~3% IPC uplift with "Zen+," one can expect double-digit percentage IPC gains with "Zen 2." Higher IPC, combined with possible increased core counts, higher clock speeds, and power benefits of switching to 7 nm, complete AMD's "Zen 2" proposition.

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12 Cores at 4.6-4.7GHz with Intel level IPC for 320$? Sounds good.
 
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They haven't said anything about clocks or cores for mainstream, yet. Live stream ~
 
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They haven't said anything about clocks or cores for mainstream, yet. Live stream ~
its around 1800 core clock
 
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T4C Fantasy

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Those Zen improvements sound amazing. Crossing fingers for a 10% IPC improvement.

I may finally buy a CPU day 1.
 
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Regarding Zen 2: Yes, yes, YEEESSSSS!! *Pumps fist into the air* I'll wait until Zen 2 ships and reviews are available, but now I feel like it was a good idea to hold back on making a Ryzen rig (not that I wanted to hold back, but my country almost went straight to hell just before I pulled the trigger)

Regarding Vega: Meh, I guess, since it's not aimed at consumers. Although it's probably a lot more interesting for those that work in HPC, datacenters, cloud computing and the like.
 
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Lisa Su reemphasizing that the chiplet design decision was taken 4 years back, one heck of a gamble that & everyone from the current CEO, Mark Papermaster & quite likely Jim Keller(?) as well deserve massive accolades for it!
 
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New Epyc chiplet disposition (see the reflection):

Screenshot from 2018-11-06 19-22-31.jpg
 
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New Epyc chip disposition (see the reflection):

View attachment 110021
Nice catch, we knew it'd be 8 chiplets for 64 cores but that arrangement is new!
They also said 2x core density and a lot of confimations on leaks which wasn't said outright but confirm our leaks..

IPC is an unknown but I expect Intel levels of IPC and I doubt Intel have left any ipc on the table so I think we're close to the max possible IPC as both enter the same realm after decades of optimizations.
But thankfully memory always give IPC and that'll be on Zen3 (DDR5).

Also we do not know what the I/O chip will be in the different classes, Epyc, TR, Desktop\laptop.
Furthermore clocks, but if IPC and 4.5 ghz i think we have a pretty good cpu in the future :) (1.25x performance = frequency = 4.5 allcore possibility ~)
 

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Nice catch, we knew it'd be 8 chiplets for 64 cores but that arrangement is new!
They also said 2x core density and a lot of confimations on leaks which wasn't said outright but confirm our leaks..

IPC is an unknown but I expect Intel levels of IPC and I doubt Intel have left any ipc on the table so I think we're close to the max possible IPC as both enter the same realm after decades of optimizations.
But thankfully memory always give IPC and that'll be on Zen3 (DDR5).

Also we do not know what the I/O chip will be in the different classes, Epyc, TR, Desktop\laptop.
Furthermore clocks, but if IPC and 4.5 ghz i think we have a pretty good cpu in the future :) (1.25x performance = frequency = 4.5 allcore possibility ~)
Better shot:

Screenshot from 2018-11-06 19-22-31.png

The chiplet arrangement seems odd but i'm no expert on the matter.

The good thing is that the NUMA thing seeems to be gone, meaning in TR CPUs and Epyc CPUs will have the whole chip running certain things that required "legacy mode", or whatever it's called, will no longer need it. I'm assuming the bigger AM4 platform Zen 2 version (in cores) will also not require NUMA, which is quite good, i think.
 
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Been holding back on a new system build for a couple years now due to mining craze and RAM price fixing but it looks like next year will finally be the year to make the jump!

No more excuses for not building a Ryzen system next year, lower price with close to/same/or possibly above IPC of Intel chips means there's hardly anything to sacrifice for red team. Of course, always wait for reviews kids ;-) !
 

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So a single PCB & 9 chiplets spread out, I wonder how they're connected without the interposer :confused:
Hadn't noticed the lack of interposer. Wondering the same, really.

Intel is a victim of their own increased frequencies: with the higher and higher base / boost frequencies for the current manufacturing processes, they either come up with a significant boost in IPC and reduce the clocks or improve the clocks and keep (or slightly improve) the IPC and they assumed they could do the former with 10nm but that backfired spectacularly and they are being forced to use an even more refined version of the same process and that means pretty much the same IPC, meaning they need higher clocks on these than the previous gen, which in turn aggravates the issue with frequencies / IPC for the next gen.

AMD must be careful not to fall for the same "frequency trap" or they risk getting caught in it. I'd prefer CPUs with lower frequencies but higher IPC than CPU with high frequencies but lower IPC, so long as the performance ends up being roughly the same, ofc.
 
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So a single PCB & 9 chiplets spread out, I wonder how they're connected without the interposer :confused:
Well the same, a silicon interposer is not that different from a pcb, it's going to have quite a few layers though.
I said it for years interposers appeared with sockets as an abstraction layer to connect the beol to a socket and as such has Always been a multi leyer(phones tut it got it right seconds before) circuited PCB not just a interlink.
Am4 could be one of the best sockets ever made and shows intel why people like me aren't spending cash with them.
 
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So a single PCB & 9 chiplets spread out, I wonder how they're connected without the interposer :confused:
Perhaps is not functional, who knows?
So the chiplets were true, now let's wait the reviews.
Will these Rome be compatibles with the same motherboards as current EPYC?
 
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Well the same, a silicon interposer is not that different from a pcb, it's going to have quite a few layers though.
I said it for years interposers appeared with sockets as an abstraction layer to connect the beol to a socket and as such has Always been a multi leyer circuited PCB not just a interlink.
Am4 could be one of the best sockets ever made and shows intel why people like me aren't spending cash with them.
Yes but some of the previous assumptions dealt with a possibility of active(?) interposer IIRC, in this case the distance between the (core) chiplets & the I/O chiplet might produce more interesting results. I have a feeling that the 2 chiplets near each other might act as the current desktop ryzen, with 8 cores per CCX & chiplet, or something like that.
Perhaps is not functional, who knows?
So the chiplets where true, now let's wait the reviews.
Will these Rome be compatibles with the same motherboards as current EPYC?
Possibly, they're still fine tuning the chips that's for sure. The clocks weren't final & so we didn't see too many hard numbers, except a couple of demos. Yes, socket compatible.
Infinity Fabric (2nd Gen IF) ;)
Yeah but would be nice to see some more details.
 
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Numbers, I want numbers, they mean something. Their cache latency has been their biggest issue, that and memory controller issues.
 

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Idk, I'm rather disappointed. This wasn't aimed at the consumers at all :(
 
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Idk, I'm rather disappointed. This wasn't aimed at the consumers at all :(
It was already announced that EPYC would come first. Mostly, this is important because all or most of the architecture changes and enhancements will carry over Ryzen's next launch, which I think could happen somewhere around Q1 or Q2 2019 (maybe)

EDIT: Yeah, maybe that's too hopeful...
 
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It was already announced that EPYC would come first. Mostly, this is important because all or most of the architecture changes and enhancements will carry over Ryzen's next launch, which I think could happen somewhere around Q1 or Q2 2019 (maybe)
Except nothing that will carry over to Ryzen has been announced. Because I highly doubt we'll get 8 channel RAM on consumer parts. It's AMD's show, I'm not faulting them. I was just saying, I had other expectations.

Edit: I also don't see anything about Zen2 availability in the server space, so good luck with that "Q1 or Q2 2019" prediction.
 
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Certainly an exciting set of announcements on the CPU side. Hard to tell what the GPU side will look like though. I do applaud AMDs approach if they have truly pulled it off. As transistor count skyrockets, it makes sense to going back to separate dies to improve production. It allows AMD to properly harvest and leverage certain uniform blocks (CPU modules), while customizing the IO and MC based on the application. An 8C desktop machine won’t need 8 memory channels, and the consumer won’t have to pay for some sort of cut-down “one size fits all” solution. I wonder if we’ll see a similar approach to APUs? Zen2 + GPU fed off HMB2? Can’t wait to see what they put out into the market.
 
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