AMD Zen 4c Not an E-core, 35% Smaller than Zen 4, but with Identical IPC

[AusWolf]

100% agreed

They used higher density cache (and less of it) which is something the OS doesnt know or care about, so all those core types appear the same.
The only thing needed is something the chipset driver already does, with a way to push games onto cores with higher cache if available

That's the thing - all cores have the same amount of cache. The only thing that differs is the density of circuits and the resulting clock speed difference. The scheduler only needs to know which cores are faster, which it already does since preferred cores were invented with Intel's 11th gen and Zen 3.

 

[Mussels]

It's the cores that are much denser. The L3 seems to be the same.

The article linked mentioned they used denser SRAM? as part of the cache. I'd have to re-read again

 

[Squared]

The article linked mentioned they used denser SRAM? as part of the cache. I'd have to re-read again

SRAM is what processor cache is usually made of. The alternative is DRAM which is much slower and I can only remember it being used for L4 cache in Broadwell.

As I recall, Bergamo, the 128-core server die, has denser SRAM cells making up its L3 cache. But I don't recall Phoenix 2—the 2 Zen4 + 4 Zen4c mobile die—having denser cache. My guess is it uses the regular-density L3 cache that other Zen 4 products use.

 

[AnotherReader]

The article linked mentioned they used denser SRAM? as part of the cache. I'd have to re-read again

I wasn't clear; doing the maths reveals that both the L2 and L3 are as dense as regular Zen 4. Some other SRAMs in the core use denser cells.

To save area, AMD has replaced these 8T dual-port bitcells with a new 6T pseudo dual-port bitcell developed by TSMC.