Backside power delivery CPU's

[FoulOnWhite]

Just saw a article about Backside Power Delivery, basically, digging channels in the silicon and ebedding the power supply channels below the transitor and data layers. Pretty interesting, and won't be long till every CPU is built like this. I wonder if TSMC is already working on this.
https://spectrum.ieee.org/next-gen-chips-will-be-powered-from-below

https://spectrum.ieee.org/backside-power-delivery

Seems to make perfect sense.

 

[DavidC1]

Intel's version is PowerVia coming in 20A with Arrowlake CPUs end of 2024/early 2025. They demonstrated Intel 4 with PowerVia few months ago. Intel 4 is the process being used in Core Ultra "Meteorlake" CPUs. The Intel 4 PowerVia version is essentially testing to derisk for 20A.

TSMC is coming with backside power delivery in the N2 variant with production in 2026.

 

[delshay]

Looks promising, but I would like to also see the death of DIMM sockets, ie bring the memory significantly closer to the CPU with massive reduction in trace length.

 

[DavidC1]

I remember this is a backside power delivery thread? Not "put ram behind the CPU" thread?

 

[FoulOnWhite]

I remember this is a backside power delivery thread? Not "put ram behind the CPU" thread?

Indeed sorry

 

[DavidC1]

Indeed sorry

I'm not talking about you, but @delshay