Not quite. Take a look at this board:
https://rog.asus.com/sk/motherboards/rog-strix/rog-strix-x670e-a-gaming-wifi-model/spec/
It has two CPU-bound M.2 slots, otherwise Gen 5.0 speeds would be impossible through chipset. There are no notes regarding shared bandwidth, so there should be no slots with shared bandwidth.
Zen 4 or Zen 5 along with AM5 have:
- 16 PCIe Gen 5.0 lanes dedicated for GPU, can be divided to x8/x8 via PCIe switch
- 4 PCIe Gen 5.0 lanes dedicated to NVMe M.2 storage
- 4 PCIe Gen 5.0 lanes for general purpose (meaning mobo maker can decide how to utilize them)
- 4 PCIe Gen 5.0 lanes for interconnection with chipset, those lanes operate in Gen 4.0 mode, since chipset only supports PCIe Gen 4.0
I'ts 28 lanes. On X870(E) mobos 4 GP lanes are utilized by ASMedia USB 4.0 controller (2 lanes per port). So, if user occupies 2nd CPU-bound M.2 slot, then lanes from GPU x16 slot gets divided into x8 and x8. 4 lanes from x8 are used for the 2nd M.2 drive, other 4 are wasted. GPU will have 8 lanes.
This is the difference between X670(E) and X870(E) chipset. On X870(E) due to must have USB 4.0 support, GPU lanes get sacrified when 2nd M.2 slot (CPU-bound) is populated. On X670(E) GPU slot remains to have full 16 lanes along with 2x4 lanes for M.2.
This is why I say forget about X870(E) if you don't need USB4. X670(E) provides USB 3.2 which is perfectly sufficient for 99% of users.