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Bifurcation

H

Hankieroseman

Joined
Aug 30, 2020
Messages
411 (0.24/day)
In my understanding of building the fastest performing computer bifurcation can make a difference which is why I have a Gamer limited to the Flight Simulator.
I would like to see those maps again showing the lanes for a particular motherboard. So in this configuration there are no shared lanes and the GenZ.2 slot has it's own lanes. at G5.0x4. Correct?
This example is ASUS ROG Crosshair X670E EXTREME
 

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That's what it says.

Shoutout for doing things old school BTW (print pages, write on the prints, scan to PDF, post the scans).
 
PCIEx16_1 and M.2_1 are connected directly to the CPU so there are no lane splitting if you use just those two. There are no precise information in the manual regarding the GEN-Z.2 module lanes. Only that GEN-Z.2_1 is connected to the CPU and GEN-Z.2_2 is connected to the chipset.

But since the CPU have 28 built-in PCIe lanes, grouped as x16/x4/x4 connections (last x4 goes to the chipset). It is fair to assume that the GEN-Z.2_1 slot is directly connected to the second x4 connection.
 
It comes down to CPU (and therefore, motherboard) architecture.

I did quite a lot of study of (Intel 1851 first) motherboards to ID which would allow me have 2 x PCIe5.0 SSD's running, without stealing from the GPU. Turns out none. This is due to a limitation of PCIe5.0 lanes on the supporting chipset. You can only have 1 x PCIe5.0 SSD......and several PCIe4.0 SSD's on this architecture.

And very similar on AMD too.....they have a different architecture, but it too has the same limitations.

Most motherboards, therefore, have such a dedicated slot for 1 x PCIe5.0 SSD, as well as (undesired) Bifurication ones, for additional.....at the cost of lanes for the GPU.
 
Not quite. Take a look at this board: https://rog.asus.com/sk/motherboards/rog-strix/rog-strix-x670e-a-gaming-wifi-model/spec/

It has two CPU-bound M.2 slots, otherwise Gen 5.0 speeds would be impossible through chipset. There are no notes regarding shared bandwidth, so there should be no slots with shared bandwidth.

Zen 4 or Zen 5 along with AM5 have:
- 16 PCIe Gen 5.0 lanes dedicated for GPU, can be divided to x8/x8 via PCIe switch
- 4 PCIe Gen 5.0 lanes dedicated to NVMe M.2 storage
- 4 PCIe Gen 5.0 lanes for general purpose (meaning mobo maker can decide how to utilize them)
- 4 PCIe Gen 5.0 lanes for interconnection with chipset, those lanes operate in Gen 4.0 mode, since chipset only supports PCIe Gen 4.0

I'ts 28 lanes. On X870(E) mobos 4 GP lanes are utilized by ASMedia USB 4.0 controller (2 lanes per port). So, if user occupies 2nd CPU-bound M.2 slot, then lanes from GPU x16 slot gets divided into x8 and x8. 4 lanes from x8 are used for the 2nd M.2 drive, other 4 are wasted. GPU will have 8 lanes.

This is the difference between X670(E) and X870(E) chipset. On X870(E) due to must have USB 4.0 support, GPU lanes get sacrified when 2nd M.2 slot (CPU-bound) is populated. On X670(E) GPU slot remains to have full 16 lanes along with 2x4 lanes for M.2.

This is why I say forget about X870(E) if you don't need USB4. X670(E) provides USB 3.2 which is perfectly sufficient for 99% of users.
 
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