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Does TS affect (BIOS) LLC values? / Where is my IA Voltage Offset in HWInfo?

streesH2

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Nov 3, 2023
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Hi,
  1. I´ve set loadline calibration (LLC) to level 2 (1.46 milliohms) on my asus mainboard to keep overshots quite low. Does any TS 'tuning' affect this value?

  2. Looing at HWInfo, sometimes the adaptive voltage offset values (CPU Core / CPU P Cache) will be shown correctly under IA Voltage Offset . But sometimes HWInfo reports 0,000 and I only can see a value under "CLR (CBo/LL/Ring) Voltage Offset", even when I restart HWInfo / TS. Where is my IA value gone? Just a HWInfo issue?
 
Post some ThrottleStop FIVR screenshots so I can see your settings.

HWiNFO is accurate but it does not update in real time. That can be confusing if you do not know this. Use the FIVR voltage monitoring table. It does not have these issues.

I am not sure how TS and the LLC settings interact on your motherboard. I use LLC on my Asus desktop board and TS voltage control works on top of that. VID Support has to be enabled in the BIOS.
 
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I use LLC on my Asus desktop board and TS voltage control works on top of that.
Sounds great so far! It´s a z690-i (of course I could also do UV directly on the board, espacially on this board ;-))

HWiNFO is accurate but it does not update in real time. That can be confusing if you do not know this. Use the FIVR voltage monitoring table. It does not have these issues.
Uh! I will have a look on it.
 

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The FIVR monitoring table shows offset voltage values (-0.1055) for both the Core and the P Cache so that seems to be working correctly.

Intel CPUs have a single register that all voltage requests have to go through. Both reading and writing all six voltages to the CPU as well as quite a few other FIVR items all go through this one register. When you have multiple programs all accessing this same register at the same time, it is possible that there could be interference between different programs. Usually restarting HWiNFO will get HWiNFO to properly update the FIVR voltages but due to limitations of the Intel design, there is always the possibility of conflicts. The FIVR monitoring table in ThrottleStop updates every second and is usually correct.
 
Thx for explaining :)

Coming back to LLC:
So the only way to check if there is interaction between BIOS LLC and TS would be to UV that much, that the OS will crash, then set LLC 2 to (let´s say) LLC 4 and check if OS is stable now. Right?

Do you know which voltage is affected by TS? Can´t find "CPU Core" / "CPU P Cache" in BIOS. Is there a way to map TS settings into BIOS speech? IMHO BIOS represents the physics (see picture taken from overclockers.net) which is the base for all and at the end everything tools like TS do, will be translated into the "real" world. Pls correct me if I´m wrong.
 

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Can´t find "CPU Core" / "CPU P Cache" in BIOS.
Most BIOS versions only list the CPU voltage as a single entry. There are two separate registers within the CPU. The BIOS sends this one value to both the core and P cache registers separately. ThrottleStop allows you to adjust these two voltages individually.

This has proven to be beneficial when running some software like Cinebench on some Intel processors. Being able to set the core offset to a larger negative value compared to the cache offset seems to be a trick that reduces voltage when a CPU is running AVX instructions. Cinebench uses mostly AVX instructions so this program has proven to be a good way to test if using two different voltages is a good thing to be doing. Many laptop users that are either power or thermal limited get better Cinebench scores when using two different offset voltages.

In my Asus BIOS it is SVID Support that I have enabled.

When I lower the load line values, my CPU gets less voltage. This means when I am using ThrottleStop to undervolt, I need to undervolt my CPU less so it maintains stability. The lower load line values are already undervolting my CPU. The ThrottleStop undervolt is in addition to that.

I use the TS Bench when playing around with voltages. When you adjust the voltage, the TS Bench test will usually start reporting errors within a few seconds when you have gone too far with your undervolt settings. If the TS Bench reports any errors, stop the test immediately. Errors indicate that the CPU needs more voltage usually before it is so bad that Windows crashes.

On my motherboard, the VCore voltage reported by HWiNFO confirms that the undervolt being applied by ThrottleStop is working.

1702143074395.png
 
Thx a lot, that really helps!

Btw 01:
I just saw that CPU Core offset is frequently alternating between 0,0000 and the value I set. This happens approx. every 1-3 seconds. CPU P Cache does not alternate. TS Bench does not show any errors.
I changed UV to -117,2 (both CPU Core and P Cache). Now the display is alternating between 3 values: 0,000 -> 0,105 (value before) -> -0,1172 (new value) -> 0 and so on ....
HWINFO shows 0,105 in IA Offset and 0,1172 in CLR (CBo/LL/Ring) Voltage Offset.

It seems the values are not written correctly / not to both registers / missbaviour of caching values? Very strange ...

(I guess this at least explains why HWINFO showed 0,0000 --> at the moment when I started HWOINFO 0,0000 was a real value).

Update: Now I restarted Windows. First there was 0,0000, no alternating. When I ran the bench, alternating returned, now with 0,0000 and 0,1172 (0,105 has gone).

Btw 02:
TS Bench seems to run the efficient cores only? (Tasmgr shows that / Temps are increasing on efficient cores only)

Update: When running the bench with infinite time, all cores are involved. But not all the time, I would say 30% of benching time. Value alternating (Btw 01) now each second.
 

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I just saw that CPU Core offset is frequently alternating between 0,0000 and the value I set.
That usually means you have some other software on your computer writing to the CPU voltage control register. Can you think of any manufacturer's control software that is running in the background? XTU perhaps? Exit any other monitoring programs including HWiNFO. Too many programs reading and writing data to the single control register can cause interference.

TS Bench seems to run the efficient cores only?
That is too bad. That used to be a decent quick test for 11th Gen and previous CPUs. I have heard of issues with the scheduler where you have a pile of unused P cores that are not being taken advantage of. Your testing proves that problem does exist.
 
No, XTU never has been installed on this machine (would love to stick with TS). And there is no piece of Asus SW as far as I know. I'm not at home at the moment, will check it tomorrow. Do you have any hints how to figure out what is writing to the register?
 
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Do you have any hints how to figure out what is writing to the register?
There is no easy way to figure out what software is writing to that register. It could be a driver. You can post a screenshot of the Task Manager. Perhaps I will get lucky and see something that might be causing the problem.

It seems the values are not written correctly
No one else has ever reported this problem. That is why I think it is something on your computer.

There should be no reason to check the Clock Mod box on the main screen of ThrottleStop. I have not seen any computer in many years use clock modulation throttling.
 
Ok, I will check everything. WIN powerplan too, I was playing around with that and made some adjustments. Maybe I messed it up. Also want try to find the process which writes to the register with procmon.
No one else has ever reported this problem
Sounds great :ohwell:
no reason to check the Clock Mod box
Ok.
 
After I checked everything in autostart (apps, drivers, etc.), resetted the WIN-powerplan and much more (without success), I desperately gave XTU a try. This is the result (issue with alternating values in FIVR -> CPU CORE value):

There are 4 values:
1 Power Core
2 Efficient Core
3 Power Core Cache
4 Efficient Core Cache
(and some others which are not important for this case)

When setting a value for undervolting offset for Power Core (1), the value Efficient Core (2) remains untouched (0,0000). Now TS begins to alternate between these two values (1 + 2), the (via TS successful modified) P Core (1) and the still untouched E Core (2). This means TS can READ both values, but you cannot SET the (important?) Efficient Core (2) value via TS.
Why splitting Cache into P und E (3 +4), but not the Core (1 +2) in the GUI? If it´s intended always to write both (P/E Core values), then we have a bug here. At least when using a board/CPU combo like mine.

Alternating between 3 values:
Today, with XTU installed it I could reproduce it more often then yesterday without XTU. To be honest, I could not reproduce it 100%. To me it seems that these registers where the values are stored, can store more than only 2 values (P Core / E Core) or there is any caching inbetween, no idea. But I think there is definitely something wrong ... I could set three different values and TS could read them all!
 
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then we have a bug here.
Thanks for the feedback. Without access to any Intel FIVR documentation and with no 13th Gen hardware for testing purposes, I am not too surprised that ThrottleStop has a few bugs. I am not sure why you are the first person to notice these issues. No one else has ever reported the core offset in the monitoring table alternating back to 0.0000 like you are seeing.

This means you cannot set the (important?) Efficient Core (2) value via TS at all.
Most people running 13th Gen HX mobile processors are happy with their results using TS 9.6 to undervolt only the P cores. I am guessing that they would be even happier if they could undervolt both the P and the E cores. Maybe someday when I get some new hardware I will look into this further.

Exit ThrottleStop and continue using XTU or the BIOS to adjust your voltages.
 
Exit ThrottleStop and continue using XTU
... or continue using TS without E cache ;-)
XTU would be the very last solution. It eats 500 MB RAM for something that can be done with a lightweight app.
or the BIOS
rather this.

Take care :)
 
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