This may sound stupid but I wonder if Vram works like reg ram in that it has multiple stable clock steps. You know 1333, 1600, 1866? Someone should call sapphire for me.
Good question. I was originally thinking, since the VRAM voltage isn't software adjustable on my card, perhaps they've given me just enough volts to stabilize @ 1850MHz, yet not too much to keep it stable @ 1500MHz. Though, after some invenstigating on the matter, I'm now thinking there's probably quite a bit more to it than that. I've just found some very interesting info on what's technically refered to as
clock frequency and data rate scalability. I mean it actually runs just as stable @ idle too(300MHz). So what's with that? Someone should definitely call Sapphire...for us both.
But until then, here's a quote from page 8 of the
Qimonda GDDR5 –White Paper 2007 to help explain what I'm talking about.
7. GDDR5 Power management
The GDDR5 is designed in a way to only consume power when really needed. Several features and methods are implemented in a way to allow a demand driven power management.
Extreme wide clock frequency range and data rates
Multi level, demand driven termination enabling
Low power modes for DRAM core
Low supply voltage of 1.5V
Data and address bit inversion
Power-down and self refresh modes
Scalable clock frequency and data rate
GDDR5 allows the system to dynamically scale the memory I/O data rate according to the workload. The I/O data rate of GDDR5 can be gaplessly varied from 5 Gbps down to 200 Mbps (50 MHz clock frequency). Towards lower frequencies the PLL is turned off for additional power saving.
Low power strobe mode
For lower frequencies the GDDR5 interface can be set to a low power strobe mode. In this case, the GPU can turn off the clock data recovery reducing the power consumption. For data alignment in the strobe mode, the DRAM sends out a strobesignal via the EDC pins together with the data.
Low power mode for DRAM core
Additionally to the I/O frequency scaling, the GDDR5 DRAM core offers a low power mode for operation at lower frequencies. The low power mode is initiated by a low power bit set from the controller.
Multi level termination
Signal termination is necessary to match impedances of transmission lines and improve signal quality. But termination consumes also power. At lower data rates, the signalling gains more and more margin which allows to operate the system with partially matched termination impedance. GDDR5 allows to double the termination impedance for slower data rates or even turn it off. Termination can be adjusted separately for data bus, command & address bus and WCK clock to take maximum advantage of the power saving potential.
Data and address bit inversion
The data and address bit inversion feature does reduce the power consumed by the termination resistors and output drivers. The GDDR5 high level termination scheme only consumes power if the transmission line is driven to Low. As data and address bit inversion effectively reduces the amount of LOW signals on the data and address bus, it reduces the average power consumption as well.
Notice the terms "
Extreme wide clock frequency range..." and more specifically "
...GDDR5 can be gaplessly varied from 5 Gbps down to 200 Mbps (50 MHz clock frequency).
That's just how they've been labeling it lately. What they really mean by that is "1250MHz x 4".
MSI claims my 280X Gaming 3GB has even faster "
GDDR5 6000MHz Memory". Which equals, as stated previously, the stock 1500MHz(x 4 since GDDR5 is "quad-pumped").
http://www.msi.com/product/vga/R9-280X-GAMING-3G.html#hero-overview