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Intel, Micron First to Sample 3-Bit-Per-Cell NAND Flash Memory on 25 nm Process

Discussion in 'News' started by btarunr, Aug 17, 2010.

  1. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Oct 9, 2007
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    Hyderabad, India
    Intel Corporation and Micron Technology Inc. today announced the delivery of 3-bit-per-cell (3bpc) NAND flash memory on 25-nanometer (nm) process technology, producing the industry's highest capacity, smallest NAND device. The companies have sent initial product samples to select customers. Intel and Micron expect to be in full production by the end of the year.

    The new 64-gigabit (Gb) 3bpc on 25nm memory device offers improved cost efficiencies and higher storage capacity for the competitive USB, SD (Secure Digital) flash card and consumer electronics markets. Flash memory is primarily used to store data, photos and other multimedia for use in capturing and transferring data between computing and digital devices such as digital cameras, portable media players, digital camcorders and all types of personal computers. These markets are under constant pressure to provide higher capacities at low prices.

    Designed by the IM Flash Technologies (IMFT) NAND flash joint venture, the 64-Gb, or 8 gigabyte (GB), 25nm lithography stores three bits of information per cell, rather than the traditional one bit (single-level cell) or two bits (multi-level cell). The industry also refers to 3bpc as triple-level cell (TLC.)

    The device is more than 20 percent smaller than the same capacity of Intel and Micron's 25nm MLC, which is currently the smallest single 8GB device in production today. Small form-factor flash memory is especially important for consumer end-product flash cards given their intrinsic compact design. The die measures 131mm² and comes in an industry-standard TSOP package.

    "With January's introduction of the industry's smallest die size at 25nm, quickly followed by the move to 3-bit-per-cell on 25nm, we continue to gain momentum and offer customers a compelling set of leadership products," said Tom Rampone, Intel vice president and general manager of Intel NAND Solutions Group. "Intel plans to use the design and manufacturing leadership of IMFT to deliver higher-density, cost-competitive products to our customers based on the new 8GB TLC 25nm NAND device."

    "As the role of NAND memory continues to escalate in consumer electronics products, we see the early transition to TLC on 25nm as a competitive edge in our growing portfolio of NAND memory products," said Brian Shirley, vice president of Micron's NAND Solutions Group. "We are already working to qualify the 8GB TLC NAND flash device within end-product designs, including higher-capacity products from Lexar Media and Micron."
    Last edited by a moderator: Dec 23, 2015
    mlee49 says thanks.
  2. WarEagleAU

    WarEagleAU Bird of Prey

    Jul 9, 2006
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    Is this what they are going to be using in the gen 3 drives that was posted on here yesterday?
    10 Year Member at TPU
  3. mlee49


    Dec 27, 2007
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    Very nice video there. He explains quite a bit and the implications are abundant with these technologies.

    This should be the key component to seeing XSD sizes of 1TB SD card.
  4. devguy


    Feb 17, 2007
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    Definetly cool for something portable like CF or SDHC/XC. But I hope we don't see that technology in SSD HDDs. The wear leveling per cell in an MLC probably averages around twice that of an SLC cell in the same timeframe (similar usage). Making a cell TLC will likely wear it around twice as fast as an MLC cell. That could mean drastically shorter lifetimes for SSD drives (not even counting the theortical performance drop from an MLC to a TLC). Although I am glad that the guy in the video did at least bring up these trade offs.
    10 Year Member at TPU
  5. happita


    Aug 7, 2007
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    "The performance and the endurance as measured in the number of times you can program the NAND tend to degrade as we increase more bits per cell"...

    Not very appealing.....not at all :mad:
  6. zads New Member

    Sep 23, 2008
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    San Jose, Ca
    Its actually an exponential decrease of wear endurance as you go up in bits-per-cell;
    SLC to MLC to TLC
    and wear endurance decreases as you go to smaller process technologies (50nm->34nm->25nm etc).
    The result is that in our testing, the limit of these flash cells is on the order of 100-300 write cycles.
    So.. not for any SSDs (Gen 3 or otherwise).
    Only for XDHC SD cards and the like flash memory cards, to push down the $/GB.

    Most 25nm-class flash will be MLC, just that the ECC correction requirement for the SSD controller will be high higher than current requirements for 34nm flash chips.

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