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Intel, Micron First to Sample 3-Bit-Per-Cell NAND Flash Memory on 25 nm Process

btarunr

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#1
Intel Corporation and Micron Technology Inc. today announced the delivery of 3-bit-per-cell (3bpc) NAND flash memory on 25-nanometer (nm) process technology, producing the industry's highest capacity, smallest NAND device. The companies have sent initial product samples to select customers. Intel and Micron expect to be in full production by the end of the year.

The new 64-gigabit (Gb) 3bpc on 25nm memory device offers improved cost efficiencies and higher storage capacity for the competitive USB, SD (Secure Digital) flash card and consumer electronics markets. Flash memory is primarily used to store data, photos and other multimedia for use in capturing and transferring data between computing and digital devices such as digital cameras, portable media players, digital camcorders and all types of personal computers. These markets are under constant pressure to provide higher capacities at low prices.

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WarEagleAU

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#2
Is this what they are going to be using in the gen 3 drives that was posted on here yesterday?
 
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#3
Very nice video there. He explains quite a bit and the implications are abundant with these technologies.

This should be the key component to seeing XSD sizes of 1TB SD card.
 
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#4
Definetly cool for something portable like CF or SDHC/XC. But I hope we don't see that technology in SSD HDDs. The wear leveling per cell in an MLC probably averages around twice that of an SLC cell in the same timeframe (similar usage). Making a cell TLC will likely wear it around twice as fast as an MLC cell. That could mean drastically shorter lifetimes for SSD drives (not even counting the theortical performance drop from an MLC to a TLC). Although I am glad that the guy in the video did at least bring up these trade offs.
 
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#5
"The performance and the endurance as measured in the number of times you can program the NAND tend to degrade as we increase more bits per cell"...

Not very appealing.....not at all :mad:
 

zads

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#6
Its actually an exponential decrease of wear endurance as you go up in bits-per-cell;
SLC to MLC to TLC
and wear endurance decreases as you go to smaller process technologies (50nm->34nm->25nm etc).
The result is that in our testing, the limit of these flash cells is on the order of 100-300 write cycles.
So.. not for any SSDs (Gen 3 or otherwise).
Only for XDHC SD cards and the like flash memory cards, to push down the $/GB.

Most 25nm-class flash will be MLC, just that the ECC correction requirement for the SSD controller will be high higher than current requirements for 34nm flash chips.