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Intel, Samsung, TSMC Reach Agreement for 450mm Wafer Manufacturing Transition

malware

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#1
Intel Corporation, Samsung Electronics and TSMC have reached agreement on the need for industry-wide collaboration to target a transition to larger, 450mm-sized wafers starting in 2012. The transition to larger wafers will enable continued growth of the semiconductor industry and helps maintain a reasonable cost structure for future integrated circuit manufacturing and applications.


The companies will cooperate with the semiconductor industry to help ensure that all of the required components, infrastructure and capability are developed and tested for a pilot line by this target date.

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panchoman

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#2
wait so intel cpus are going from 45nm to 450 mm in 2012?
 

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#3
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#4
wait so intel cpus are going from 45nm to 450 mm in 2012?
Isn't 450mm supposed to be the size of the wafer that has the CPUs in?

EDIT

malware beat me to the punch ...
 
Last edited:

kwchang007

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#5
wait so intel cpus are going from 45nm to 450 mm in 2012?
The wafers, like discs of silicon, they produce the chips on is getting bumped up from 300mm to 450 mm.

Edit: I got beat like twice XD
 

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#6
Hehe, that's what people mean by 450mm wafer, not CPU die.

ohhhhhhhhhhhh okay for a second i was like wtf :wtf:

so what exactly will this affect?
 
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#7

kwchang007

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#8
ohhhhhhhhhhhh okay for a second i was like wtf :wtf:

so what exactly will this affect?
They can produce more cpu's per wafer, and that saves money....somehow idk the specifics.
 
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#10
Bigger wafers and smaller dies mean more cores per wafer I would assume. The die size will be down to 22nm by 2012, so they must be moving towards lots of specialized cores or something.
 
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#11

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#12
Moore's law is running out...
 

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#13
Moore's law is running out...
Shhhh don't tell Intel that. It'll keep going, until they can't shrink dies anymore, then they'll have a problem.
 
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#14
Yeah, its got a couple of years left though I presume. It might not get smaller than 22nm (the proposed shrink for the sandy bridge (successor to nahalem)). I dunno, I'm getting this off wiki, we'll just have to see I guess.
 

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#15
Yeah, its got a couple of years left though I presume. It might not get smaller than 22nm (the proposed shrink for the sandy bridge (successor to nahalem)). I dunno, I'm getting this off wiki, we'll just have to see I guess.
Well they have to go somewhere eventually. I think once we hit that wall companies are going to shift their attention from performance per watt to performance per transistor. Cause honestly they're going to only be able to stuff so much stuff in so much real estate. Or maybe they'll branch off into quantum computers which are supposed to have so much more capabilities if we could unlock them.
 
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#17
Isn't IBM already at 32nm?

There's other material they can use to shrink past 22nm anyways. Not to mention Quantum computing will be coming into style in another 10 years or so. That should kick it up a few notches for Moore and his silly law.
 

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#18
does that means more heat?
 

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#19
omg...
i have seen a 450mm-ceramic-wafer on Semicon in Munich 8 years ago. this thing is huge.

i think, it's very difficult to handle such big wafers.
- they must be thicker than 300mm, so that they do not break so easily
- you need new carriers for production (act. 300mm: 25 wafers in 1 FOUP = heavy)
- you need new tools
....
 
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#20
Shhhh don't tell Intel that. It'll keep going, until they can't shrink dies anymore, then they'll have a problem.
Aye -- though all it means is that by that point the individual sockets on our MB's we'll be dealing with will start to get bigger and bigger and bigger... :p Or the chips themselves will get a lot thicker, either way.
 
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#21
Shhhh don't tell Intel that. It'll keep going, until they can't shrink dies anymore, then they'll have a problem.
when the reached the minium size i geus the start increas the cpu size it zelf so more transistors fits on it
 

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#22
Well the problem with bigger chips means you need bigger sockets, more power, more heat is released, more cooling is need, the list goes on. The reason why we've seen such huge jumps in computing power relative to size and power consumption is because they can shrink dies. Then it'll cost more per chip and you need better interconnection stuff, yeahh bad stuff.
 
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#23
wow! that's goign to be much more efficient. It'll reduce costs and emissions, not to mention reduce the man hours of manufacturing a set number of chips. talk about an ouch day for amd. lol