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Intel's Process Roadmap Gets Updated with Plans to go Back to Two Year Cadence

No, its not, nothing in the 14nm Intel process is in 14nm and nothing in 7nm TSMC process is in 7nm (not even close xD)

Little correction : The fin width is 8nm (on intel 14nm) and 6nm (on TSMC 10 and 7nm) but we can extrapolate that on intel 1.4nm, the fin width won't be that small (and it's just the width anyway).



I just read the source document, there is no talk about number of atoms, no talk about metal layers and no talk about copper transistors. So i guess you just made that up?

And i dont claim to be an enthusiast, i am one.

And i would really want to lay off the harsh sauce, but as you can see, you guys aren't helping me...


Nah, copper atoms have a radius of .128nm so at 1.4nm there will be approximately 12, as 1.4 / .128 = 10.9 plus when packed as a metallic crystal lattice plus the variation of etch in the traces means approximately 12 atoms wide traces.


I suppose I did make all of this up, all CPU transistors contain tiny people, trapped and forced to learn math..... It's a huge conspiracy.
 
I'll be happy for Intel to go back to their tick-tock both companies making good progress each year would be nice. I'll believe it when I see it though...
 
Well, I'm glad at least the roadmap is back to a two year cadence...
 
I love it - "Easiest Path Design" when they can't design anything that works with the size nodes shown (Well, except 10nm) but definitely no easy way out of that node going foward!

Backport opportunity is just another escape hatch to find solid ground when their research efforts blow up in their face like it's been as of late.
Optimal cost (Profit) path they're still wishing for shown.
EUV and "New Features", "New Features", "New Features", ....... What new features?
Would be beyond sad to say that in...... 2025 right?

This looks like a thing taken from one of the boardroom meeting slideshow presentations and posted here.
I mean seriously, that's what it looks like.
"new features" does look like someone made a template and couldn't get answers from R&D or who ever they're asking to fill in the blanks. Seems like that's the spot for things like "gate-last" "double-patterning" "finfet" things of that nature.

The whole slide reeks of someone was told to make a slide so a slide was made
 
Jokes about Intel's tick tock tock tock tock tock tock+ cadence aside, it's interesting to see how much refinement can be done at the same process level. When we inevitably hit the lowest size we can get with silicon it's good to know we will still see performance increases while new tech is developed.
 
Yes, "backporting", aka fix bugs on CPUs allowing users to perform simple CPU swaps on existing or older hardware without needing to upgrade their entire system to a new platform with its own feature set of bugs. Should have been committed to as soon as meltdown hit the industry. Goodwill, trust, brand loyalty, lost through Intels poor policy decisions at the time.
 
It's amazing to me that a company like Intel could drop the ball so hard. They dropped the ball in a murky lake and their dive teams can't find it. :rolleyes:
 
"new features" does look like someone made a template and couldn't get answers from R&D or who ever they're asking to fill in the blanks. Seems like that's the spot for things like "gate-last" "double-patterning" "finfet" things of that nature.

The whole slide reeks of someone was told to make a slide so a slide was made
There ya go.
That accounts for one who actually delivered on time and earned their pay.

It's amazing to me that a company like Intel could drop the ball so hard. They dropped the ball in a murky lake and their dive teams can't find it. :rolleyes:
o_O
:roll:
Gee - You just qualifed for the R&D team.
Namely for being the guy that gets to decide what lake it is so R&D can tell the board "something" is in development whenever asked about it.

I hear that pays well..... For now.
 
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