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Lynx Point USB 3.0 Controller Issue Correction Needs New Hardware

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#26
There's not too much difference between S2 and S3, but I wonder if this will affect Hybrid sleep transitioning to S4. Pretty sucky for mobile users, which is where I envision Intel was targetting Haswell.

Desktop I imagine should be pretty much unaffected. They'll either be ON, OFF or maybe in S4 Hibernate. I've never seen anyone use the normal S2/S3 save-to-RAM sleep modes for desktop.
 
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#27
Who would be stupid enough to buy this?

The very idea that I have a faulty chip in my room won't allow me to sleep soundly.
Then be prepared to never go to sleep, as I have news for you: ALL chips have errata, plain and simple. :shadedshu It is inevitable, unless we achieve perfection ourselves, which is pretty much impossible with current technology.
 
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#28
There's not too much difference between S2 and S3, but I wonder if this will affect Hybrid sleep transitioning to S4. Pretty sucky for mobile users, which is where I envision Intel was targetting Haswell.

Desktop I imagine should be pretty much unaffected. They'll either be ON, OFF or maybe in S4 Hibernate. I've never seen anyone use the normal S2/S3 save-to-RAM sleep modes for desktop.
thats not true, i cant even remember the last time i turned off my computer, i just leave it there and it goes to sleep after a while, and I almost always have a hard drive connected especialy that i do alot of work with photoshop/illustrator/maya/mudbox and many times i work with the files in the external that way i dont waste to much time transfering big files
 
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#29
Then be prepared to never go to sleep, as I have news for you: ALL chips have errata, plain and simple. :shadedshu It is inevitable, unless we achieve perfection ourselves, which is pretty much impossible with current technology.
I know everything is not perfect... by "not perfect" I mean poor efficiency, not fast enough etc. but that doesn't mean they don't work as they are supposed to. For example USB 2.0, it is slower than USB 3.0 so it is getting replaced, but it does what it is supposed to do without any glitch.

Here, Intel is promising to provide USB 3.0 support... so I expect full USB 3.0 support, not errors when I do something particular.
 
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#30
AMD please wake up
 
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#31
I know everything is not perfect... by "not perfect" I mean poor efficiency, not fast enough etc. but that doesn't mean they don't work as they are supposed to
Then you still haven't grasped what 1c3d0g is saying.
You will find errata in every AMD chipset
You will find errata in every AMD CPU
You will find errata in every Intel chipset
You will find errata in every Intel CPU....and every other processor you can think of
For example USB 2.0, it is slower than USB 3.0 so it is getting replaced, but it does what it is supposed to do without any glitch
Not necessarily (as I outlined earlier), and USB2.0 is arguably a bigger deal since the vast majority of USB devices in use are 2.0/1.1 specification.
 
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#32
haswell is a SOC so its most likely on the cpu
and its too late for intel to fix this because they already started ramping up haswell production a long time ago lol, so they would need to get rid of a huge number of chips, or disable usb3.0 and sell these chips as pentiums and celerons lol
not to mention after the problem is fixed on paper it takes over a month for a wafer to be ready
and the last thing intel wants to do is release haswell at the same time as kaveri and steamroller
Haswell is not any more SOC than ivy bridge is, at least on non ultrabook platforms.

The USB 3.0 controller on the CPU. I think, but maybe not.
If its Lynx I would think it's on Motherboards, but sense they said Haswell I would think CPU.

To be honest I'm not 100% sure. I thought Motherboards at first, but when they say " Intel's upcoming "Lynx Point" 8-series core logic" It makes me think it's a CPU problem.

EDIT: more about Lynx http://www.techpowerup.com/160702/I...-Chipset-Detailed-Completely-SATA-6-Gb-s.html
USB3 is integrated into the southbridge still, not the cpu. That would be a waste of die space.
 
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#33
lets hope amd takes the home run, dont think intel will pull another netburst but these screw ups amd should totaly take advantage of, adverstise like mad and pull a rabit out of the hat please
its obvious intel dont wanna delay haswell that way they can have a couple quarters with minimal competition as richland wont be a game changer performance wise, but maybe in graphics will keep things in check, steamroller and kaveri on the other hand is the big unknown, could be another bulldozer, or another k8. kaveri being the first true apu with hsa features and the begining of the new amd after all the restructuring and what not, it sure will be an interesting year, and intel please keep bringing more screw ups like this, maybe that will keep you from getting too cocky, and will help amd land a punch on ur face to knock down these prices a bit. shiz its been 2 years since i brought my i5 2500k and price/performance remained steady ever since. heck piledriver was probably the only improvement in price/performance but that was only in multithread/multitasking
 

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#34
USB3 is integrated into the southbridge still, not the cpu. That would be a waste of die space.
Intel no longer has a south bridge. The USB controller exists on the PCH or off the PCH using one or more of the PCI-E links off the chipset like with several X79 boards. USB 3.0 isn't integrated into X79 but the ASMedia chip does just fine.
 

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#36
The pch is just a renamed southbridge afaik.
The PCH is all the components that used to be on both the north bridge and south bridge prior to Intel switching to an IMC with the exception of the memory controller and the bulk of PCI-E lanes. Intel more moved some of the larger functionality to the CPU and merged everything else into one chip. The PCH works a lot differently than a south bridge would alone though.
 
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#37
Before, northbridge was only responsible pci/pci-e/agp, memory controller and possibly integrated graphics. All those functions are now on the cpu die.
 

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#38
Before, northbridge was only responsible pci/pci-e/agp, memory controller and possibly integrated graphics. All those functions are now on the cpu die.
PCI-E and the memory controller moved to the CPU yes, but PCI-E still exists on the chipset. It has more features of a south bridge, yes, but it's not strictly what was considered a south bridge. Otherwise they wouldn't have altered the name to reflect something different.
 
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#40
Then be prepared to never go to sleep, as I have news for you: ALL chips have errata, plain and simple. :shadedshu It is inevitable, unless we achieve perfection ourselves, which is pretty much impossible with current technology.
Yes, all chips have errata, but usually only those don't get fixed that son't cause major problems or only under rare circumstances. This one might affect quite a few systems since today S3 is used heavily an many only use S3/S4 instead of shutdown, especially laptops. It causes Problems with Readyboost or just any flashdrive or flashcard, too.

Haswell is not any more SOC than ivy bridge is, at least on non ultrabook platforms.
Oh yes it is, Intel will introduce some SoC variants of Haswell, the PCH integrated on package, with PCIe removed an DMI substituted with a special link.

The PCH is all the components that used to be on both the north bridge and south bridge prior to Intel switching to an IMC with the exception of the memory controller and the bulk of PCI-E lanes. Intel more moved some of the larger functionality to the CPU and merged everything else into one chip. The PCH works a lot differently than a south bridge would alone though.
PCI-E and the memory controller moved to the CPU yes, but PCI-E still exists on the chipset. It has more features of a south bridge, yes, but it's not strictly what was considered a south bridge. Otherwise they wouldn't have altered the name to reflect something different.
Nope, the PCH is every last bit the former ICH. Only difference is the FDI, the Flexible Display Interface, to output the CPU-graphics to VGA/DVI/HDMI/Displayport. All components from the former MCH were moved to the CPU, first memorycontroller (with Nehalem on S1366, the main PCIe-Controller remaining in the X58), then main PCIe-controller (with Lynnfield on S1156, then yet connected internally with QPI like on S1366, since sandy fully integrated on DIE). It is exactly the same with AMD on FM1/FM2 with the FCH.
 
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#42
Ultrabooks rely even more heavily on USB3.0 than desktops since they usually only have a small amount of flash memory and no ODD. So the errata is even more relevant there.
 

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#44
Nope, the PCH is every last bit the former ICH. Only difference is the FDI, the Flexible Display Interface, to output the CPU-graphics to VGA/DVI/HDMI/Displayport. All components from the former MCH were moved to the CPU, first memorycontroller (with Nehalem on S1366, the main PCIe-Controller remaining in the X58), then main PCIe-controller (with Lynnfield on S1156, then yet connected internally with QPI like on S1366, since sandy fully integrated on DIE). It is exactly the same with AMD on FM1/FM2 with the FCH.
The ICH never offered PCI-E off of it. That was the MCH's job and you're right. On Sandy Bridge the PCI-E controller was moved to the CPU. There is one flaw with your logic. The PCH still has PCI-E lanes on it. Not as many as the CPU, no, but it does still exist and the point of the MCH was to get everything in the ICH plus features here and there from the MCH as they become more SoC like by consolidating components. If you have a skt1155 or skt2011 board, you have 8 PCI-E lanes coming off your chipset. I think skt1155 is limited to only using 4 of them with 4 being internally used inside the chipset for other things though.

A good example is my motherboard, the P9X79 Deluxe. The PCH PCI-E lanes are used to drive other components on the board such as USB 3.0, eSATA, Bluetooth and Wi-Fi, the second Realtek lan port and the extra SATA 6Gb controller that are not integrated into the PCH.

The point is, that is not strictly a renamed ICH. It's more of a bastard child between the MCH and the ICH, which it just happened to inherit more traits from the ICH because that was the step Intel decided to take but to say it's strictly what the ICH used to be isn't true.
 
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#45
Nope, your Information is flawed. All ICHs for S775 since ICH6 had between 4 and 6 PCIe-Lanes integrated for periphals and expansion slots, while the MCH contained sixteen to 32 (X38/48) of them for graphics or non at all on specific IGP-chipsets. Since DMI is PCIe based you could say the ICH had in fact 8 to 10 Lanes integrated.

This is the reason why crossfire wasn't very useful on P965 or P35, where Intel only allowed a secon mechanical x16 slot, being electricaly x4 and linked to the ICH. So it was limited to only 1GB/s bandwith plus it had to take a detour via the ICH to MCH via DMI, then to the first GPU. Not that it would have been impossible to split the 16 Lanes from the MCH to 2x8, it only needs some switch ICs and no extra logic in the MCH to do that, but Intel did only allow that on 975X.

Now with Ibex Peak (P55/H57 etc.), this was increased to 8 Lanes (12 with DMI included), while X58 still used ICH10 like P45 etc. With cougar Point, the Lanes were updated to support PCIe2.0 (500MB/s instead of 250MB/s), so DMI went up to DMI 2.0 with 2GB/s instead of 1GB/s, too.

Now X58 and X79 are a bit special, because both have spare lanes in the IOH (X58, 40 Lanes 2.0 total, 4 for DMI, 32 for graphics, leaving 4 for periphals) or the CPU (S2011, 44 Lanes 3.0 total, 4 for DMI, 32 for Graphics, leaving 8 for periphals). This is were your board comes in. Don't know exactly what, but part of the expansion slots and chips should be connected directly to the CPU insted of the PCH (expansion slots and SATA 6Gb/s would benefit the most).

Since 8 Lanes for Periphals and expansion Slots in S1156/1155 is a bit low these days, most manufacturers use an 8 Lane PCIe-Switch from PLX, connected to one or more Lanes from the PCH and switching between several expansion slots and chips. This will be a bottleneck if the chips connected use more bandwith simultaneously than the connection to the PCH.

The point is, apart from the FDI routing the display signals from the IGP in the CPU out, the PCH is exactly a renamed ICH, albeit with more or faster generations of everything. You would only have to google a block diagram for any S775 chipset and compare it with a S1155 chipset to confirm what I'm talking about.
 
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#46
Nope, your Information is flawed. All ICHs for S775 since ICH6 had between 4 and 6 PCIe-Lanes integrated for periphals and expansion slots, while the MCH contained sixteen to 32 (X38/48) of them for graphics or non at all on specific IGP-chipsets. Since DMI is PCIe based you could say the ICH had in fact 8 to 10 Lanes integrated.
Your information once again is flawed. I used to have a skt775 with a 975X Express MCH which had an ich7 south bridge IIRC.

Motherboard: MSI 975X Platinum Power Up
Chipset: 975X Express
Southbridge: ICH7DH

The 975X has 16 lanes and the ICH has... PCI? Maybe I'm missing something here or maybe you're wrong? By the way ICH7DH on this board is the 820801GDH.

ich7.PNG
 
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#47
For christ's sake, google block diagrams. Specs on intel homepage ar mostly unusable since they don't give much information most of the time. Every ICH form 6 to 10 had 4 to 6 PCI Lanes for Expansion slots and chips.
 

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#49
well i was under the impression that haswell was an soc with pretty much everything integrated on board, guess i was wrong loool
All they have is CPU and GPU and busses, so no SoC's there. There are very few (if any?) x86 SoC's afaik.
 
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#50
All they have is CPU and GPU and busses, so no SoC's there. There are very few (if any?) x86 SoC's afaik.
as far as i remember the south bridge was to be integrated next so idk

also now we know usb 3 has problems, but is it because of the usb controller or is it the cpu sleep states that needs to be fixed? because ivy had usb3.0 and it didnt have that problem