Simple question about GPUs releases....

[RatusNatus]

Why Nvidia and AMD are releasing GPUs made in 5nm process while there are 3 nm process available?

 

[eidairaman1]

Why Nvidia and AMD are releasing GPUs made in 5nm process while there are 3 nm process available?

Send both companies that question

 

[Draconian]

Because you'll buy the current card for over 2k and then buy their next card for likely 2.5k or more. The companies don't have an interest in selling the consumer "the best" they have - they sell what they know you'll buy while keeping future cards in the pipeline. Their interest is to keep tech incremental - sell you upgrades again and again - instead of selling you "the last gpu you'll ever need".

 

[N/A]

With 50 series out of the bag. 60 series for sure.

 

[AusWolf]

Why Nvidia and AMD are releasing GPUs made in 5nm process while there are 3 nm process available?

My best guess is cost. GPUs are expensive as they are, no need to make them cost even more.

My second best guess is that 3 nm probably isn't mature enough, yields not good enough. This hasn't stopped Nvidia before, that's why it's only my second guess.

 

[sLowEnd]

Why Nvidia and AMD are releasing GPUs made in 5nm process while there are 3 nm process available?

Cost/availability

It's not uncommon for high bidders like Apple to buy up most or all of the capacity of new nodes, and new nodes are pretty expensive

 

[N/A]

Since it's all happening in the same fab. Only a matter of adjusting the machines. So I don't buy it. No excuse not to use the best possible node that is only 1000$ more expensive per wafer. Even if it was 2X more expensive the video cards are so expensive now that it wouldn't even be felt at all. So they weren't ready with the shrink or whatever, because the blueprint has to be designed first and that costs a ton of money. If they can get away with it eg. 750mm2 die, that is not even maxing the reticle limit yet they're going to keep postponing the move. 858mm2 30K CUDA cores with 40 GBps being totally possible could carry on for another generation, but I hope not.

 

[AusWolf]

Since it's all happening in the same fab. Only a matter of adjusting the machines. So I don't buy it. No excuse not to use the best possible node that is only 1000$ more expensive per wafer. Even if it was 2X more expensive the video cards are so expensive now that it wouldn't even be felt at all. So they weren't ready with the shrink or whatever, because the blueprint has to be designed first and that costs a ton of money. If they can get away with it eg. 750mm2 die, that is not even maxing the reticle limit yet they're going to keep postponing the move. 858mm2 30K CUDA cores with 40 GBps being totally possible could carry on for another generation, but I hope not.

How much more expensive do you want GPUs to get?

 

[londiste]

My best guess is cost. GPUs are expensive as they are, no need to make them cost even more.

My second best guess is that 3 nm probably isn't mature enough, yields not good enough. This hasn't stopped Nvidia before, that's why it's only my second guess.

Also, the N3 variation for high performance stuff seems to be N3P which looks like is slated to come at the end of 2025.

Apple is doing the biggest N3 dies right now and they are mostly on high density libraries (using FinFlex, so P-cores seem to be on performance library). M4 still has lower transistor count than say RTX5070 or 7800XT.

Since it's all happening in the same fab. Only a matter of adjusting the machines.

That is a VERY naive way of looking at it. Moving a fab from 5nm class process to a 3nm class process technically can be described as adjusting the machines (although as far as I know it does also involve replacements). What it does not accurately describe is the cost of this - both in terms of adjusting/replacing equipment as well as lost time (we are taking about several months if not quarters).

Best possible node only $1000 more expensive per wafer is not true either. The difference is much bigger and that is not taking into the account the defect rate and resulting yields from dies big enough for GPUs.

Edit:
Food for thought - Nvidia's biggest baddest datacenter Blackwells with GB100 dies are also on 4N. These are at a reticle limit and - at least within enterprise version of reason - the cost is no object...

 

[Assimilator]

Since it's all happening in the same fab. Only a matter of adjusting the machines.

That's not how any of this works, do some basic research before making statements that show how ignorant you are.

that is only 1000$ more expensive per wafer

It's not.

Even if it was 2X more expensive

It's not.

 

[Zach_01]

Why Nvidia and AMD are releasing GPUs made in 5nm process while there are 3 nm process available?

RDNA 4 is on 4nm but to answer the question I have to say that with companies its all about max profit.
To maximize profit they have to choose between expenses and pricing

A smaller/newer/latest node wafer is not only more expensive but with worse yields than the previous ones. And the larger your chips are, it's even worse for yielding.
Also availability of each node is a key factor.

 

[DirtyDingusMcgee]

I'd still like to know how they are getting around the quantum tunneling issues inherent in stuff this size (5nm and below)

I've read all the stuff about MoS2 and carbon nanotubes, but it still seems pretty experimental.

I'm no quantum physicists or anything, but there has to be some trick to it, because they have always been pretty sure of issues at that tiny a scale.

 

[TumbleGeorge]

I'd still like to know how they are getting around the quantum tunneling issues inherent in stuff this size (5nm and below

The "5" is just advertised trading name of node not actual number of nanometers in CPU elements dimensions.

 

[iameatingjam]

Well as nodes mature yields go up.... so taking on the most cutting edge node might not make sense when you need to make huge pieces of silicon and also you are trying to balance things like cost,margin/price, performance gain/ gain per $ ( though seems like nvidia is getting comfortable taking advantage of their position at the top and forgetting about that last one at times...) Anyway, it just comes down to money like always. Also, GPUs have more real-estate and cooling capacity for... just making a bigger die or just giving it more power than say a smartphone.

 

[Wirko]

I'd still like to know how they are getting around the quantum tunneling issues inherent in stuff this size (5nm and below)

I've read all the stuff about MoS2 and carbon nanotubes, but it still seems pretty experimental.

I'm no quantum physicists or anything, but there has to be some trick to it, because they have always been pretty sure of issues at that tiny a scale.

Maybe they can effectively minimise that with the right combination of materials for the insulation, passivation, barrier and other layers. Also, low voltages.

 

[freeagent]

I would like to know how they will appease the masses within 6 months. Pricing should be horrendous until the first round and a half of customers has been served. After that it will just be another meme.

Edit:

But I don't care either so.. I guess shut up and take my money

 

[Wirko]

The "5" is just advertised trading name of node not actual number of nanometers in CPU elements dimensions.

That's true but the layers I mentioned above are actually only a few nm thick. IBM made a 2 nm test chip in 2021 and they published nicely annotated, coloured and dimensioned x-ray images. It was obvious that some layers were roughly 2 nm thick. Here's the part that I can still find:

IBM Unveils World’s First 2 nm Chip Technology - Semiconductor Digest

IBM announced a breakthrough in semiconductor design and process with the development of the world’s first chip announced with 2 nm nanosheet technology. The new design is projected to achieve 45 percent higher performance and 75 percent lower energy use than today’s 7 nm chips. It will likely...

www.semiconductor-digest.com

 

[iameatingjam]

I'd still like to know how they are getting around the quantum tunneling issues inherent in stuff this size (5nm and below)

I've read all the stuff about MoS2 and carbon nanotubes, but it still seems pretty experimental.

I'm no quantum physicists or anything, but there has to be some trick to it, because they have always been pretty sure of issues at that tiny a scale.

As @TumbleGeorge was getting at, it could be other manufacturing improvements that aren't necessarily just smaller transistor gate length, but yet need a new nice round name. And we know actual transistor measurements have been divorced from reality for a while now. But I admit, I am not sure.

 

[TumbleGeorge]

That's true but the layers I mentioned above are actually only a few nm thick. IBM made a 2 nm test chip in 2021 and they published nicely annotated, coloured and dimensioned x-ray images. It was obvious that some layers were roughly 2 nm thick. Here's the part that I can still find:

IBM Unveils World’s First 2 nm Chip Technology - Semiconductor Digest

IBM announced a breakthrough in semiconductor design and process with the development of the world’s first chip announced with 2 nm nanosheet technology. The new design is projected to achieve 45 percent higher performance and 75 percent lower energy use than today’s 7 nm chips. It will likely...

www.semiconductor-digest.com

I read article 12.25 times difference between area density 7nm to 2nm if numbers are real but only

The new design is projected to achieve 45 percent higher performance and 75 percent lower energy use than today’s 7 nm chips.

Although I tend to believe in science, I didn't draw these arrows limiting a given size. I didn't hold an actual ruler graduated in nanometers across a slice of the transistor.

 

[DirtyDingusMcgee]

I didn't hold an actual ruler graduated in nanometers across a slice of the transistor.

This. I know just enough physics to understand that it works like the math says it will, but once things get into single digit nanometers ( or quantum), it somehow loses some of the realness that i usually enjoy about physics.

Perhaps i am a caveman, but i like to be able to examine things with my senses, and not being able to freaks me out a bit.

There are a lot of new things coming along that you can't ever touch. Ai is one of them. Don't get me started on quantum computers. I can follow the math (with some help) but it still seems like magic.

 

[N/A]

That's not how any of this works, do some basic research before making statements that show how ignorant you are.
It's not.
It's not.

How not, the numbers floating around are $17,000 for N5 $18,000 N3. The problem is in increasing production.
And I will make a prediction that A16 is 199.9M / mm² density and costs twice as much.

 

[RandallFlagg]

How not, the numbers floating around are $17,000 for N5 $18,000 N3. The problem is in increasing production.
And I will make a prediction that A16 is 199.9M / mm² density and costs twice as much.

That is just the cost of the physical wafer. Below should give some idea of that additional cost vs N5.

Keep in mind, in the financial world there is an opportunity cost of capital deployed. What this means is, If I am investing $28B into my business and it will take me 2 years to start getting a return, that 2 years of lost potential returns on say a 5% treasury bill also counts (which would be ~5B in 3 years). The technical definition is : "...the opportunity cost of capital is the incremental return that one foregoes by investing the capital in an internal project rather than investing it in a marketable security. " This calculation gets much worse if you are using debt to fund the expansion.

Edit: Also, 60%+ of the cost of production is not in the wafer.

So all of these costs add up. In Taiwan, they spent $17B retro-fitting an existing fab to get N3 going. Fab 21 in the below chart is new and can't do N3 yet afaik. TSMC production is still mostly on N5 and its derivatives, by a pretty wide margin.