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TSMC 20 nm and CoWoS Design Infrastructure Ready

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TSMC announced today that the readiness of 20 nm and CoWoS design support within the Open Innovation Platform (OIP) is demonstrated by the delivery of two foundry-first reference flows supporting 20 nm and CoWoS (Chip on Wafer on Substrate) technologies.

TSMC's 20 nm Reference Flow enables double patterning technology (DPT) design using proven design flows. Leading EDA vendors' tools are qualified to work with TSMC 20 nm process technology by incorporating DPT aware place and route, timing, physical verification and design for manufacturing (DFM). The new silicon-validated CoWoS Reference Flow that enables multi-die integration to support high bandwidth, low power can achieve fast time–to- market for 3D IC designs. The CoWoS flow also benefits designers by allowing them to use existing, mainstream tools from leading EDA vendors.

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