Hi, all
I have been reading a lot of these posts on the net, and thought I could try to explain what 1T and 2T command timing does in a layman term, so in the future you can impress your friends with your knowledge. I get this info because I have done many DDR4 memory board designs in the past involving high end digital processing system. This is from an EE designer's perspective.
The DDR4 system has two separate connection buses when communicating between the memory controller and the RAM modules. One set of connection is called the command/address bus, which provide commands from the controller to the RAM module, the same bus connection is shared between all DDR4 memory chips. The other set of connections are data bus connections, DDR4 RAM chips are normally 4, 8 or 16 bit wide, to form the 64 bit wide memory bus on a modern 64 bit CPU memory bus, 16, 8 or 4 memory chips are required. These memory chips have separate data bus connections to the controller, which means when reading and writing from the actual DRAM cell holding the information, the connection from controller to the RAM is point to point. The same command and address are needed at all memory chips to form the 64 bit word, meanwhile the number of pins on both the controller and the RAM module need to be minimized as not to require a HUGE board to connect controller to the ram chips, as a result, the command/address line between the controller and the ram chips are shared in a daisy chain fashion.
For anyone with basic electronics knowledge, a signal traveling fast down a tire need to have the same impedance along its path of travel as not to scatter the signal along the way. However, the daisy chained command/address connections become split when more RAM modules are installed on a motherboard. The more the impedance is split between all the installed modules the more the impedance along the signal path drifts further away from the desired value, causing more signal scattering along the path. The motherboard designer can only set the termination on the DRAM controller to better fit a particular setting and they tend to optimize their setting when only two RAM modules are used, because that's the more common case for most users. This allow two RAM module to run faster clock speed and run faster command (1T command).
When 4 module of RAM are install in a MB vs 2, the signal is more scattered on the cmd/add bus between controller and RAM chips, which means it would take longer for a voltage on the cmd/add line to settle to allow the controller and the RAM chip to recognize the voltage on those connections.
1T command rate means the command/address bits on the cmd/addr bus are allowed 1 single clock cycle to complete, a 2T command rate means the command/address bits are allowed two clock cycles to settle and be recognized. Changing command rates from 1T to 2T simply allow the controller and ram chips more time to settle and properly recognize the command and address locations being sent between them.
This is also why 1T timing would work with a slower RAM clock, because 1 single clock cycle on a 1600MT/s clock is twice as long as a single clock cycle on a 3200Mt/s clock , but turning on 2T timing simply means the controller would allow 2 clock cycle to pass between each command/address bit, allowing the RAM chips to properly decipher the command and address being sent at 3200Mt/s as if they were being sent at 1600Mt/s.
1T and 2T command rate doesn't really affect modern DDR4 performance all that much because the command and address are often being set with bank and rank interleaving. In a simplified view, interleaving means the longer time it takes between 1T and 2T command rate rarely impact the read/write performance from the overall RAM chips all that much, because while the command/address are being set/read, data from the other parts of the RAM are being read/written, so it doesn't matter it takes longer for a 2T command timing to take 2x the time to transfer the same command from controller to the RAM chips, as it normally takes much longer for the controller to read/write data on the data bus because pre-fetching and other data bursting being done in the DDR4 system.
This is obviously a very simplified view of how 1T and 2T timing works and why often using 4 RAM modules requires 2T command timing. It is however, possible to achieve 1T timing under high clock rate even with 4 RAM modules, but this normally creates much more complexity on the MB design and make the board more expensive to design and manufacture. Given that 1T and 2T really doesn't affect the bottom line DDR4 data read/write performance all that much, most MB would tend to require 2T command timing to properly operate more RAM modules, because 2T command rate simply give the controller and ram chip more time to understand each other as more RAM modules inevitably degrade the signal quality on the DDR4 cmd/add bus.
