Opcode 0x1 was "ReadLane" in GCN1.0/1.1.you can't change the hardware otherwise you need to recompile or reinterpret in some way the instructions at the silicon level which more or less negates the advantage of not having to add complex scheduling logic on chip.
But opcode 0x1 is "Floating-point 32-bit Add" in GCN 1.2 (aka: Polaris / 400-series / 500-series.)
This sort of change requires a recompile. A summary of the opcode changes between GCN 1.0 and 1.2 can be found here: https://clrx.nativeboinc.org/wiki2/wiki/wiki/GcnInstrsVop2
This dramatic change in opcodes requires a recompile. Surely the reason you suggest is mistaken. Both AMD and NVidia regularly change the hardware assembly language associated with their GPUs regularly, without much announcement either. Indeed, that's why NVidia has PTX, so that they can have an assembly-like language that retargets many different machines (be it Pascal, Volta, or Turing).