Wednesday, July 20th 2011
Intel Mulls Propagating PCI-Express 2.0 x2 Interface
PCI-Express x1 met its match with the recent flood of devices such as 2-port SATA 6 Gbps and USB 3.0 controller chips that maintain their tiny package sizes thanks to a single-lane PCI-Express bus connection. The single-lane connection is already saturated with these kinds of devices: SATA 6 Gbps is moot with 250 MB/s per direction bandwidth of PCI-E 1.1, and could face bottlenecks with 500 MB/s of PCI-E 2.0, it is a similar case with USB 3.0 controllers. Use of PCI-Expresss x4, the bigger PCI-E bus standard, is a bad option as it increases PCI-E data pins by four times (significantly impacting chip package sizes), while eating into the limited lane budget of today's desktop chipsets.
The next best thing is PCI-Express 2.0 x2. While 2-lane PCI-Express is hypothetically possible, it has never been implemented by motherboard manufactures, neither on client, nor enterprise platforms. PCI-Express' parent organisation PCI-SIG doesn't have a slot or port specification for PCI-E x2, either. Intel seems to be of the idea that PCI-Express 2.0 x2 will provide immediate relief to manufacturers of small-footprint devices such as inexpensive third-party USB 3.0 and SATA 6 Gbps controllers, it provides a total of 2 GB/s bandwidth, 1 GB/s per direction, which greatly alleviates bandwidth bottlenecks, while not significanly increasing chip pin-counts. PCI-Express 3.0 is still in its infancy, while implementing PCI-Express 2.0 x2 is the easier, short-term solution. It will cause minimal R&D overhead on manufacturers to implement it. PCI-E 2.0 x2 will fit nicely into the limited lane budget of today's desktop chipsets.
Source:
VR-Zone
The next best thing is PCI-Express 2.0 x2. While 2-lane PCI-Express is hypothetically possible, it has never been implemented by motherboard manufactures, neither on client, nor enterprise platforms. PCI-Express' parent organisation PCI-SIG doesn't have a slot or port specification for PCI-E x2, either. Intel seems to be of the idea that PCI-Express 2.0 x2 will provide immediate relief to manufacturers of small-footprint devices such as inexpensive third-party USB 3.0 and SATA 6 Gbps controllers, it provides a total of 2 GB/s bandwidth, 1 GB/s per direction, which greatly alleviates bandwidth bottlenecks, while not significanly increasing chip pin-counts. PCI-Express 3.0 is still in its infancy, while implementing PCI-Express 2.0 x2 is the easier, short-term solution. It will cause minimal R&D overhead on manufacturers to implement it. PCI-E 2.0 x2 will fit nicely into the limited lane budget of today's desktop chipsets.
29 Comments on Intel Mulls Propagating PCI-Express 2.0 x2 Interface
now i have to wait for my gigabyte ga-z68x ud4 b3 and 2600k
If they want to add x2 to the PCI Express 3.0 standard, no one will really care. Adding it to PCI Express 2.0 though is a bad idea.
Like I said, they should add x2 to PCI Express 3.0 and then push for using it. It makes no sense to revise a standard whom's days are already numbered.
Third-party GbE PHY chips don't use Cougar Point's GbE port (PCI-E 1.1 x1 @ 50 MHz), they take up one of those eight PCI-E x1 lanes, if you give away that PCI-E 2.0 x4 to a single device, you're left with just 3 lanes to offer as expansion slots or drive other onboard devices.
"Putting more lanes on the chipset" means designing a new chipset right now. Not viable.
Moving to PCI-E 3.0 would mean that Intel has to redesign a chipset, plus small manufacturers like JMicron have to spend tons of money designing for a new PCI-E specification, and carrying the risk of using a specification that hasn't been validated in the market by much bigger companies (like NVIDIA, AMD, etc.). This is something small companies won't do. So the easiest solution is PCI-E 2.0 x2. There's minimal R&D and risk by both parties.
Eventually all these smaller companies we've talked about will be on PCI 3.0, along with future chipsets with support. Shoe-horning in x2 now will undoubtedly extend the adoption of 3.0.
Luckily I think the premise of this mulling is weak and nothing will come of it :)
I'm pretty sure PLX already has products for this purpose. I believe they make a switch that can take an x4 link from the chipset, and output 3 x4 links, or 1 x4 link and 8 x1 links, or just 12 x1 links.
Yes, you can make the argument that all those links are still sharing the x4 uplink bandwidth and hence won't really gain a benefit from this. However, they work just like network switches. If only one device needs the x4 bandwidth, then it gets all that bandwidth. Yes, if more devices need that bandwidth they have to share it, but if you populate most of the links with low bandwidth devices such as onboard sound and USB2.0 controllers, and secondary LAN controllers, etc, then the high bandwidth device will get the bandwidth it needs.
This is why I love my P6T6. My next board will also be a 'Workstation' type board with a similar 6/7x PCIe slots. I don't care for anything else after having one. PCI is going away and I see no reason to buy any add in card that does not have a PCIe interface. So why bother with a board that offers something I have no use for?
I know this isn't Intel, but they can bit me.