Monday, September 8th 2014

Intel Debuts the Xeon E5-2600/1600 v3 Processor Family

Intel Corporation today introduced the Intel Xeon processor E5-2600/1600 v3 product families to address the requirements of diverse workloads and the rapidly evolving needs of data centers. The new processor families include numerous enhancements that provide performance increases of up to 3x over the previous generation, world-class energy efficiency and enhanced security. To facilitate the explosive demand for software defined infrastructure (SDI), the processors expose key metrics, through telemetry, which enable the infrastructure to deliver services with the best performance, resilience and optimized total cost of ownership.

The processors will be used in servers, workstations, storage and networking infrastructure to power a broad set of workloads such as data analytics, high-performance computing, telecommunications and cloud-based services, as well as back-end processing for the Internet of Things.
"The digital services economy imposes new requirements on the data center, requirements for automated, dynamic and scalable service delivery," said Diane Bryant, senior vice president and general manager of the Data Center Group at Intel. "Our new Intel processors deliver unmatched performance, energy efficiency and security, as well as provide visibility into the hardware resources required to enable software defined infrastructure. By enabling the re-architecture of the data center, Intel is helping companies fully exploit the benefits of cloud-based services."

Enabling Software Defined Infrastructure
Software defined infrastructure (SDI) is the foundation for cloud computing. The digital services economy requires agility and scale that demands all infrastructure resources be programmable and highly configurable. These abilities, coupled with telemetry, analytics, and automated actions, allow the data center to become highly optimized. Intel continues to invest in delivering this vision of an automated data center, and with the new Xeon E5-2600 v3 product family, the company has introduced key sensors and telemetry that further enhance SDI.

The Intel Xeon processor E5-2600 v3 product family introduce new features that provide greater visibility into the system than ever before. A new cache monitoring feature provides data to enable orchestration tools to intelligently place and rebalance workloads resulting in faster completion times. This also provides the ability to conduct analysis of performance anomalies due to competition for cache in a multitenant cloud environment where there is little visibility into what workloads consumers are running.

The new processors also include platform telemetry sensors and metrics for CPU, memory and I/O utilization. With the addition of thermal sensors for airflow and outlet temperature, the visibility and control has increased significantly from the prior generation. The processors offer a holistic set of sensors and telemetry for any SDI orchestration solution to more closely monitor, manage and control system utilization to help maximize data center efficiency for a lower total cost of ownership.

Increased Performance and Energy Efficiency
With up to 18 cores per socket and 45 MB of last-level cache, the Intel Xeon E5-2600 v3 product family provides up to 50 percent more cores and cache compared to the previous generation processors. In addition, an extension to Intel Advanced Vector Extensions 2 (Intel AVX2) doubles the width of vector integer instructions to 256 bits per clock cycle for integer sensitive workloads and delivers up to 1.9x higher performance gains.

The Xeon E5-2600 v3 product family also increases virtualization density, allowing support for up to 70 percent more VMs per server compared to the previous generation processors, which helps to reduce data center operational expenses. Memory bandwidth constrained workloads will gain up to 1.4x higher performance compared to the previous generation with the support of next-generation DDR4 memory. Intel Advanced Encryption Standard New Instructions (Intel AES-NI) have also been enhanced to accelerate data encryption and decryption by up to 2x without sacrificing application response times.

The processors are built using Intel's industry-leading and energy-efficient 22 nm, 3-D Tri-Gate technology, cutting power consumption while boosting performance of transistors. The new "per-core" power states dynamically regulate and adjust power in each processor core for more power-efficient workload processing.

Combining both record performance and advanced efficiency features, the Intel Xeon processor E5-2600 v3 product family sets a new world record for server energy efficiency based on performance per watt.

Creating Open, Flexible Networks with Intel Xeon E5-2600 v3 Processors
Intel Xeon E5-2600 v3 processors can be paired with the Intel Communications Chipset 89xx series featuring Intel Quick Assist Technology to enable faster encryption and compression performance to improve security in a wide range of workloads. Service providers and networking equipment providers can use the platform to consolidate multiple communications workloads onto a single, standardized and flexible architecture to speed up services deployment, reduce costs, and create a more consistent and secure user experience.

In addition, the new Intel Ethernet Controller XL710 family helps address the increasing demands on networks with capabilities to enable better performance for virtualized servers and networks. The flexible 10/40 gigabit Ethernet controller provides twice the bandwidth while consuming half the power compared with the previous generation.

Extensive industry support
Starting today, system manufacturers from around the world are expected to announce hundreds of Intel Xeon processor E5 v3 family-based platforms. These manufacturers across servers, storage and networking include Bull, Cray, Cisco, Dell, Fujitsu, Hitachi, HP, Huawei, IBM, Inspur, Lenovo, NEC, Oracle, Quanta, Radisys, SGI, Sugon and Supermicro, among many others.

Pricing details
The Intel Xeon processor E5-2600 v3 product family will be offered with 26 different parts that range in price from $213 to $2,702 in quantities of 1,000. Intel Xeon processor E5-1600 workstations will be offered with six different parts in prices ranging from $295 to $1,723.
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12 Comments on Intel Debuts the Xeon E5-2600/1600 v3 Processor Family

#1
The Von Matrices
I find it extremely impressive that there is an 18-core part available (albeit for $3000). There may not be much progress in the desktop market but the server market is another case entirely.
Posted on Reply
#2
xvi
I'm kind of surprised to see an 18 core part available. I'm pretty sure Intel tried something like this before and found that the latency between cores killed a lot of the performance.
Posted on Reply
#3
The Von Matrices
xviI'm pretty sure Intel tried something like this before and found that the latency between cores killed a lot of the performance.
This kind of reminds me of Intel's "Project Keifer" from 2006 which was intended to compete with Sun's UltraSPARC T1. Interestingly, all of the design features discussed in that article are present in the 2014 processors.
Posted on Reply
#4
Maban
Because everyone likes die shots. They can only fit 85 of these onto a single wafer.

Posted on Reply
#5
HumanSmoke
The Von MatricesI find it extremely impressive that there is an 18-core part available (albeit for $3000).
Too conservative. List price is actually $4115.
The Von MatricesThere may not be much progress in the desktop market but the server market is another case entirely.
True enough. General efficiency will be enough to ensure Xeon platforms continue to sell well. I wonder what two 18-core E5-2699v3 plugged into a decent C612 boardmanage in Cinebench? :laugh:
Posted on Reply
#6
The Von Matrices
MabanBecause everyone likes die shots. They can only fit 85 of these onto a single wafer.
That is an interesting die layout. If they are using three rings like in the v2 processors, they must follow a convoluted path. It almost looks like they took a 12 core die and stitched 6 additional cores on the left.
Posted on Reply
#7
Maban
The Von MatricesThat is an interesting die layout. If they are using three rings like in the v2 processors, they must follow a convoluted path. It almost looks like they took a 12 core die and stitched 6 additional cores on the left.
"The SBox manages the interface between the two Rings.

The processor is composed of two independent rings connected via two sets of bidirectional buffered switches. Each set of bi-directional buffered switches is partitioned into two ingress/egress pairs. Further, each ingress/egress pair is associated with a ring stop on adjacent rings. This ring stop is termed an Sbo. The processor has up to 4 SBos depending on SKU. The Sbo can be simply thought of as a conduit for the ring, but must also help maintain ordering of traffic to ensure functional correctness in certain cases."

Posted on Reply
#10
Per Hansson
Yea I'm eyeing these.
I'm considering to buy a X99 mobo along with a 5820k now.
And then down the road when these processors come down in price have a nice upgrade path.
For example right now you can find the LGA1366 six core Xeon 5650 for around €65 on eBay, that's a fantastic bargain!

My only question is if the 5820k will work with ECC memory installed in the system, Asrock could not answer that.
(Obviously it can't utilize it but I just want to know if it will work without ECC or if it just wont boot at all...)
Posted on Reply
#11
HumanSmoke
Well, no Cinebench, but a reasonable cross section of enterprise related workload benches at Anandtech

Posted on Reply
#12
The Von Matrices
I'm amazed that the L3 cache on the 18-core CPU has 50 to 100% higher latency than the 8-core CPU from two generations ago. It seems like as you add any more cores/cache the L3 becomes less and less useful compared to just going to main memory, and the problem is getting worse as more cores/cache are added. Intel seems to have acknowledged this issue by introducing its cluster-on-die option.

I'm left to wonder if the next evolution of these many-core CPUs is to have multiple, small, fast L3 caches shared among small groups of cores and a single, large, slow L4 shared among all cores.
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