Tuesday, March 18th 2008

Nehalem to Use Similar Cache Structure to Phenom

It looks like Intel has decided to adopt the same approach as AMD with the cache structure on its upcoming Nehalem processors, opting to go for small per-core L1 and L2 caches, with a large shared L3 cache. The new architecture will feature 64KB L1 cache per-core working in the same way as current Core 2 CPUs, but instead of a shared L2 cache each core will have 256KB of its own. All of the cores will then have access to a shared L3 cache of up to 8MB. AMD’s Phenom CPUs work in a very similar manner, such as the 9600, which has 256KB L2 cache per-core and a shared 2MB L3 cache. The exclusive L2 caches give each core a pool of fast-access memory, while the shared cache acts as a buffer to trap data and instructions other cores may have requested, allowing another core to access it more quickly than using the main memory.Source: Reg Hardware
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15 Comments on Nehalem to Use Similar Cache Structure to Phenom

#1
lemonadesoda
I hope this cache strategy works. L3 cache SUCKED big time on netburst. I'd rather there was more L2 and less, or NO, L3, just L2. I'd prefer they implemented QUAD CHANNEL ram architecture to double the data bandwidth. That would mean u need to stick in 4 sticks of RAM for optimal speed.

Alternatively, they should implement a new memory design, (like back in the 90s), where L3 cache was outside the CPU die, and on cache RAM sticks on the mainboard. Easy to upgrade and configure to any size you wanted. Although external L3 is still slower than internal L3, its massively cheaper to manufacture, and if you implement QUAD or OCTO channel cache... its doable.
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#2
cdawall
where the hell are my stars
since this is finally switching to an onboard mem-controller does this mean a whole new socket or are they just swapping chipsets for this?

it would make sense to me for a whole new socket seeing how nothing will work with these chips that is currently available.
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#3
Morgoth
High end and server Nehalem cpu's wil have intergraded memmory controller
keep up the good news intel! FTW!
btw nehalem wil have 2-3 socket types
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#4
cdawall
where the hell are my stars
by: Morgoth
High end and server Nehalem cpu's wil have intergraded memmory controller
keep up the good news intel! FTW!
btw nehalem wil have 2-3 socket types
by: wikipedia

The codenames "Bloomfield" (desktop chip), "Gainestown" (server chip), "Gilo" (mobile chip), and "Beckton" (or "Becton") (server chip) have been associated with Nehalem, but with very few details
looks like 3 sockets if wiki can be believed
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#5
Morgoth
yep LGA1160 ( mobile and low end )
Socket LGA1366 ( high end desktop and server)
Socket-LS (LGA1567) ( 8 cored server cpu)
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#6
a111087
so you will need a new mobo?
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#9
ShadowFold
by: Morgoth
yep and ddr3 :)
Thats gonna be for enthusiasts only then... Unless DDR3 becomes affordable :eek:
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#10
Morgoth
i think ddr2 had its time ddr3 needs to get bether prices
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#11
WarEagleAU
Bird of Prey
If ya'll think about it. IF Intel takes their core duo and quads and takes amds kick ass strategy from a few years ago, you will have one mother of a proc, if done right without that FSB stuff. ( I hear they may use hyper threading too and semi sorta get rid of the FSB). If that is the case, woozah!!!
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#12
Morgoth
yes the will use HT and quikpath ( replaced fsb)
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#13
KBD
by: WarEagleAU
If ya'll think about it. IF Intel takes their core duo and quads and takes amds kick ass strategy from a few years ago, you will have one mother of a proc, if done right without that FSB stuff. ( I hear they may use hyper threading too and semi sorta get rid of the FSB). If that is the case, woozah!!!
Seems that Intel will be borrowing a lot from AMD, the L3 cache thing, onboard memory controller, hyper threading... Don't they have patents for this kinda stuff, it seems that intel is simply copying the innovative AMD tech.
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#14
Morgoth
since when did amd used HT ?
onboard memory controller wast that first used by ibm ?
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#15
KBD
ha ha ha, you right, confused hyper treading with hyper transport, HTT with HT.

As far as on die mem controller not sure who was the first, i know that IBM, Sun and AMD and probably others as well use it, just that AMD is so well known for it and they are the ones intel is competing with it so intel wants to do anything to make their cpus are even more attractive.
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