Nubis Communications, Inc., provider of low-latency high-density optical inter-connect (HDI/O), and Alphawave Semi (LN: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, today announced their upcoming demonstration of PCI Express 6.0 technology driving over an optical link at 64GT/s per lane. Data Center providers are exploring the use of PCIe over Optics to greatly expand the reach and flexibility of the interconnect for memory, CPUs, GPUs, and custom silicon accelerators to enable more scalable and energy-efficient clusters for Artificial Intelligence and Machine Learning (ML/AI) architectures.

Nubis Communications and Alphawave Semi will be showing a live demonstration in the Tektronix booth at DesignCon, the leading conference for advanced chip, board, and system design technologies. An Alphawave Semi PCIe Subsystem with PiCORE Controller IP and PipeCORE PHY will directly drive and receive PCIe 6.0 traffic through a Nubis XT1600 linear optical engine to demonstrate a PCIe 6.0 optical link at 64GT/s per fiber, with optical output waveform measured on a Tektronix sampling scope with a high-speed optical probe.

According to Igor's Lab, who has gotten their hands on a PCI-SIG draft engineer change notice, it looks like the not entirely uncontroversial 12VHPWR connector won't be long lived. The PCI-SIG is getting ready to replace it with the 12V-2x6 connector, which will be part of the ATX 3.1 spec and the PCI Express 6.0 spec. The new connector doesn't appear to have any major physical changes though, but there have been mechanical modifications, such as the sense pins having been recessed further back, to make sure a proper contact is made before higher power outputs can be requested by the GPU. The good news is that at least in the draft spec, the 12V-2x6 connector will be backwards compatible with 12VHPWR connectors.

One of the bigger changes, at least when it comes to how much power the new connector can deliver, is that there will be new 150 and 300 Watt modes in addition to the 450 and 600 Watt modes for the sense pin detection. The 12V-2x6 connector is rated for at least 9.2 Amps per pin and the new connectors will carry a H++ logo, with th older 12VHPWR connectors getting a H+ logo. The PCI-SIG has also added stricter requirements when it comes to the cable design and quality, which should hopefully prevent some of the issues the 12VHPWR implementations have suffered from. We should find out more details once the PCI-SIG has finalised the 12V-2x6 connector specification. In the meantime, you can hit up the source link for more technical drawings and details.

Tektronix, Inc., introduces the industry's first PCI Express 6.0 compatible Base transmitter test solution just weeks after the PCI-SIG working group released PCI Express (PCIe) 6.0 Base specifications and validation requirements. PCIe 6.0 is an important and scalable standard for data-intensive markets such as data center, artificial intelligence/machine learning (AI/ML), and high-performance computing. To meet ever growing performance demands, PCIe 6.0 standard transitions to PAM4 signaling and new innovative error correcting techniques. The Tektronix test solution includes PCIe 6.0 measurement-specific software, enhanced PAM4 DSP capabilities and noise compensation on the oscilloscope for increased accuracy of results. The Tektronix test solution for PCIe 6.0 standard is further enhanced by the industry-leading analysis tools for SNDR and uncorrelated jitter measurements which are both mandated requirements for the PCIe 6.0 standard.

The industry's first PCIe 6.0 standard transmitter validation solution is focused on serving high-performance and data-intensive markets and is available worldwide for use with DPO70000SX ATI Performance Oscilloscopes. "Tektronix' PCIe 6.0 standard test solution came to market quickly because of the company's deep involvement in the PCI-SIG working group, where it helped define the standard's measurement methodologies," said David Bouse, PCI Express Principal Technology Lead at Tektronix and PCI-SIG working group participant.

Synopsys, Inc. today announced the industry's first complete IP solution for the PCI Express (PCIe ) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. Synopsys' complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1 GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

PCI-SIG today announced that PCI Express (PCIe ) 6.0 technology will double the data rate to 64 GT/s while maintaining backwards compatibility with previous generations and delivering power efficiency and cost-effective performance. The PCIe 6.0 specification is actively targeted for release in 2021.

PCIe 6.0 Specification Features

• Delivers 64 GT/s raw bit rate and up to 256 GB/s via x16 configuration
• Utilizes PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and leverages existing 56G PAM-4 in the industry
• Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
• Maintains backwards compatibility with all previous generations of PCIe technology