Just one question, Why CPU's of both Intel and AMD, have been stock in cache L3 for so long,
I think its time to update caches to L5, (L4 was buffer for iGPU or something like that).
Or increase sizes of L1 and L2
Well, it's not like L5 would be better over L4, actually each additional cache layer is less beneficial than the previous one. The L4 implementation in Broadwell was an on-die DRAM chip, and was already approaching the latency of RAM, so at that point what good would L5 do?
But I think it's about time with some larger cache improvements. While cache sizes have remained fairly stable for Intel, both Haswell and Skylake greatly improved cache bandwidth. Skylake SP/X also changed L3 to make it non-inclusive, in contrast with other (consumer) Intel models which still contain a duplication of L2 in L3, just in case another core needs it, which is "rare". This improvement will not reach Intel's mainstream models until Tiger Lake(Willow Cove).
I think Intel and AMD should take a different approach to improving L2 and L3. L3 is a spillover cache, so it only contains data evicted from L2, but since L2 and L3 contain both data and instruction cache combined, streaming data could essentially be pushing out "more useful" instruction cache. I would prefer if L2 and L3 was split like L1 is, then it could be used more efficiently and more tightly integrated. They could also prioritize lower latency for the instruction cache and more bandwidth for the data cache, etc.
