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AMD Ryzen 3000 "Zen 2" a Memory OC Beast, DDR4-5000 Possible

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What would be clocked high enough? Memory controller is tied to memory speed but the resulting bandwidth needs to fit through IF. IF has two endpoints, the other one is in the CPU cores' chiplet. Their best bet is probably making IF wider.
Supposedly not tied strictly 1:1 now. What I meant is everything on Zen+ is 12nm. With I/O die on package @ 14nm they do not have to be tied @ 1:1 ratio.

What would be clocked high enough? Memory controller is tied to memory speed but the resulting bandwidth needs to fit through IF. IF has two endpoints, the other one is in the CPU cores' chiplet. Their best bet is probably making IF wider.
What I mean is Zen+ is all 12nm.... 14nm I/O die on package is not tied @ 1:1 ratio.
 
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Supposedly not tied strictly 1:1 now. What I meant is everything on Zen+ is 12nm. With I/O die on package @ 14nm they do not have to be tied @ 1:1 ratio.
Whether chips are made on 7nm, 12nm or 14nm process has absolutely nothing to do with this. This is an architectural or configuration decision.
 
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Nice, IF it works as expected, and if it does, could we therefore look forward to having DDR-7@10k speeds in a few years for example ???



So if this is the case, why not just replace the IF with optical or another more advanced interlink method ??
IF is already well advanced, and most likely better than most interlink methods. IF can Handle any speed you throw at it, but it seems the actual ZEN design can't at the moment.
I am sure AMD is working out a way to allow ZEN to accept faster IF speeds, and hopefully we will see much faster IF interconnect speeds with ZEN3+

What Ryzen so far benefits from with fast memory is the increased IF link speed between CCXs which should be slower no matter what memory timings or speed gets to be.
Edit: reading up on IF speeds in current Zen, I assume AMD doubled the width of IF links from CCX to RAM, otherwise the divider would also limit RAM bandwidth.
This is the entire problem and reason for introducing the divider - IF cannot run at that high a clock. There is hope that AMD has improved IF in Zen2 but we will ahve to wait and see what approach they have taken with it.
Once again, IF is not the issue here from how I read into it, the issue is that the Current ZEN CCXs cannot handle faster IF speeds, if it would, AMD would have added a multiplier where it would run IF at 2x or 3x the IMC. IF isn't the problem here people, but again ZEN is a new design, and I am sure AMD is working it out so it can accept faster IF speeds,
Nevertheless, even with the latency hit due to CCX to CCX communication, ZEN runs amazing and is king of Multi-threading. Newer ZEN designs will only add to this achievement.

AMD has decided to add a new 1/2 divider mode for their on-chip bus. When enabled, it will run Infinity Fabric at half the DRAM actual clock (eg: 1250 MHz for DDR4-5000).
I am curious to see Benchmarks & Stability Tests done on manipulating this "New 1/2 Divider Mode" if possible to pump up the IF speed and see what happens. :D:nutkick:
 
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And here I am happy with this.
 
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can FCLK be overclocked ?
I mean can you push 1:1:1 ratio higher than 3733mhz ?
 
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On what board did they hit 5k? I’m still very curious as to why mine hard walls at 4333.
Impact/formula for Asus, Godlike for MSI and Aqua for Asrock

With B-die @ 4800C14 and fclk 1900, almost match 9900K with identical memory settings
Screen Shot 07-28-19 at 01.45 AM.PNG
 
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B-die 5K DOCP with 4800C18 @ XMP





 
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I played around with DRAM Calculator over the weekend, wow ! I can really set my ram to its limits, way to go AMD ! I knew it is gonna be sweet but did not realize the potential with RAM is so huge !

last week Msi released some new bios updates and I grabbed the latest release for my B450m gaming plus, the latest release addressed memory compatibility issues, I've also noticed my post is much faster than before especially when I reboot, it was not just zen 2 compatibility issues on the older chipset but memory too, all sorted now, way to go Msi !
 
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