- Dec 25, 2020
- 1,054 (1.49/day)
- São Paulo, Brazil
|System Name||Project Kairi|
|Processor||AMD Ryzen 9 5950X 16-Core Processor (B0)|
|Motherboard||ASUS ROG STRIX B550-E (AGESA 22.214.171.124 C)|
|Cooling||id-Cooling Frostflow X 360 + Gelid GC-Extreme|
|Memory||64 GB (4x 16) Corsair Dominator Platinum ROG DDR4-3600 @ 16-17-16-34-1 1.375V|
|Video Card(s)||ASUS TUF Gaming OC GeForce RTX 3090 24 GB GDDR6X|
|Storage||WD Green SN350 480 GB (x 2)|
|Display(s)||Samsung The Frame 2022 32-inch (1080p60)|
|Case||Cooler Master MasterFrame 700|
|Audio Device(s)||EVGA Nu Audio (classic) + KZ ZSN Pro IEMs|
|Power Supply||EVGA 1300 G2 1.3kW 80+ Gold|
|Mouse||Logitech G305 Lightspeed K/DA + Logitech G840 XL K/DA|
|Keyboard||Logitech G Pro K/DA with GX Brown switches|
|Software||Windows 11 Pro for Workstations 22H2 / Nobara 36|
|Benchmark Scores||Build pic: https://i.imgur.com/yxc0HrZ.jpg|
Correct me if I am wrong, but I thought L3 across 2 chiplets had to be duplicated for core cohesion, meaning you cannot simply add up L3?
No, they are independent and fully usable, though this is not without certain drawbacks. In Zen 2 and Zen 3, L3 cache slices are tied up to a core complex (CCX), and while data can be accessed between CCXs, doing so incurs an access latency penalty.
Zen 2 had two CCXs per CCD (die), and Zen 3 streamlined this to have one CCX per CCD, as it doubled the amount of cores and associated L3 per CCX. The magic of the 5800X3D is that it is a single CCD design, so it turns out to be a very straightforward setup that won't incur the inter-CCD and inter-CCX penalties because it only has one of each.
R9 3950X: 4 cores + 16 MB L3 * 2 * 2 (4C+16M/4C+16M + 4C/16M+4C/16M), you can see here this was not the most efficient topology, i.e. imagine data on CCX4/CCD2 trying to access something on CCX1/CCD1
R9 5950X: 8 cores + 32 MB L3 * 2 (8C+32M + 8C+32M), far more efficient as few tasks ever need more than 8 cores or 32 MB of cache, so it usually manages pretty well with much fewer issues
R7 5800X3D: 8 cores + 96 MB L3, should be self explanatory, the processor can fully utilize its resources with maximum efficiency
An eventual 5950X3D would behave very much like the 5950X, except that it each CCD/CCX would have the full benefits of the 96 MB L3 (just like the 5800X3D), enabling very large data sets.