- Dec 25, 2020
- 3,498 (3.26/day)
- São Paulo, Brazil
|System Name||Project Kairi Mk. III "Lunar Tear"|
|Processor||13th Gen Intel Core i9-13900KS Special Edition|
|Motherboard||MSI MEG Z690 ACE (MS-7D27) BIOS 1.E0|
|Cooling||id-cooling Frostflow X 360 w/ Thermalright BCF and Thermal Grizzly Kryonaut Extreme|
|Memory||G.SKILL Trident Z5 RGB 32GB DDR5-6800 F5-6800J3445G16GX2-TZ5RK @ 6400 MT/s 30-38-38-38-70-2|
|Video Card(s)||ASUS ROG Strix GeForce RTX™ 4080 16GB GDDR6X White OC Edition|
|Storage||2x WD Green SN350 480GB + 1x XPG Spectrix S40G 512GB NVMe + 4x WD VelociRaptor WD3000HLFS 300GB HDDs|
|Display(s)||LG OLED evo G3 55' - 4K 120 Hz HDR supremacy|
|Case||Cooler Master MasterFrame 700 in bench mode|
|Audio Device(s)||EVGA Nu Audio (classic) + Sony MDR-V7 cans|
|Power Supply||EVGA 1300 G2 1.3kW 80+ Gold|
|Mouse||Razer DeathAdder Essential Mercury White|
|Keyboard||Redragon Shiva Lunar White|
|Software||Windows 11 Enterprise 23H2|
|Benchmark Scores||"Speed isn't life, it just makes it go faster."|
Correct me if I am wrong, but I thought L3 across 2 chiplets had to be duplicated for core cohesion, meaning you cannot simply add up L3?
No, they are independent and fully usable, though this is not without certain drawbacks. In Zen 2 and Zen 3, L3 cache slices are tied up to a core complex (CCX), and while data can be accessed between CCXs, doing so incurs an access latency penalty.
Zen 2 had two CCXs per CCD (die), and Zen 3 streamlined this to have one CCX per CCD, as it doubled the amount of cores and associated L3 per CCX. The magic of the 5800X3D is that it is a single CCD design, so it turns out to be a very straightforward setup that won't incur the inter-CCD and inter-CCX penalties because it only has one of each.
R9 3950X: 4 cores + 16 MB L3 * 2 * 2 (4C+16M/4C+16M + 4C/16M+4C/16M), you can see here this was not the most efficient topology, i.e. imagine data on CCX4/CCD2 trying to access something on CCX1/CCD1
R9 5950X: 8 cores + 32 MB L3 * 2 (8C+32M + 8C+32M), far more efficient as few tasks ever need more than 8 cores or 32 MB of cache, so it usually manages pretty well with much fewer issues
R7 5800X3D: 8 cores + 96 MB L3, should be self explanatory, the processor can fully utilize its resources with maximum efficiency
An eventual 5950X3D would behave very much like the 5950X, except that it each CCD/CCX would have the full benefits of the 96 MB L3 (just like the 5800X3D), enabling very large data sets.