Dumb question about DDR5...

[trparky]

I thought all DDR5 was supposed to have ECC.

 

[P4-630]

It's just not the same as server ECC memory.

On-die ECC (Error Correction Code) is a new feature designed to correct bit errors within the DRAM chip. As DRAM chips increase in density through shrinking wafer lithography, the potential for data leakage increases. On-die ECC mitigates this risk by correcting errors within the chip, increasing reliability and reducing defect rates. This technology cannot correct errors outside of the chip or those that occur on the bus between the module and memory controller housed within the CPU. ECC-enabled processors for servers and workstations feature the coding that can correct single or multi-bit errors on the fly. Extra DRAM bits must be available to allow this correction to occur, as featured on ECC-class module types such as ECC unbuffered, registered and load reduced.

DDR5 Memory Standard: An introduction to the next generation of DRAM module technology - Kingston Technology

DDR5 is the 5th generation of Double Data Rate Synchronous Dynamic Random Access Memory, aka DDR5 SDRAM, which is available in Q4 2021. It brings better performance, stability and efficiency compared DDR4.

www.kingston.com

 

[A Computer Guy]

I thought all DDR5 was supposed to have ECC.

It has on-chip ECC in order to work. To the best of my understanding it's not a "feature" as it is required in order for the DDR5 technology to work. The transfer across the bus to and from the CPU is not included like what we previously known as ECC RAM that also includes reporting of ECC errors assuming compatible support from CPU and motherboard when installed or system halting or rebooting when an uncorrectable error occurs.

 

[qubit]

Here's more technical info on DDR5. As @P4-630 explained, DDR5 ECC is internal to it to correct for imperfect operation and is invisible to the CPU.

DDR5 SDRAM - Wikipedia

en.wikipedia.org

 

[trparky]

OK, I get it now. It has ECC internally, not externally to the CPU.