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Intel Core Skylake Processors Freeze Under Certain Workloads, Company Issues Fix

cadaveca

My name is Dave
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I did a bit of homework on this issue.

I'm a bit of a bios modder in my free time.

It appears this issue got fixed with Skylake Microcode update 56 (that's hexidecimal 56), possibly even earlier, I didn't test every version, but patching my bios with that microcode fixed this issue.

Here's the kicker: Microcode update 56 came out 10-24-2015. That's right, almost 3 months ago.

Yep, Intel has had this fixed for a while... Not sure if @btarunr wants to note that or not. ;)

Meanwhile, nearly all skylake boards I played with have old revisions down in the 30-4A range. My gigabyte board I use was particularly low. No idea why the board vendors do this, but they really dropped the ball here.

So blame the board vendors... for not actually using the code intel releases.

I'm skilled enough to patch the microcode on most bioses to the right version if anyone wants to contact me and accept the "if it's bricked it's not my fault" policy etc etc.

Here's a relevant screenshot. Before applying intels proper microcode, this would've crashed long ago:

View attachment 71029


If you can combine the non-K OC bits with this MC update... We needs to have a chat. I'll be PM'ing you about this soon.
 
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Now I feel much better for going with the older Haswell-E instead. I don't want "unpredictable behavior" under stress.
What makes you believe Hasswell-E doesn't have any bugs?
 
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What makes you believe Hasswell-E doesn't have any bugs?
It actaully has more eratta than is presently known in Skylake, but this is not unusual. Eratta generally gets noticed more as a platform ages. He is correct that the platform is far more mature, and thus errata is generally known and patched.
 
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I still wonder how exactly (well, in human speech :p) they work around bugs like this. Disable specific instructions in the CPU maybe?
 
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I still wonder how exactly (well, in human speech :p) they work around bugs like this. Disable specific instructions in the CPU maybe?
They don't disable entire instructions usually if that's what you mean. It's worth noting a machine as complex as a modern cpu has literally hundreds of KNOWN eratta issues. Most of these are insignifigant and get worked around via microcode, albeit usually prior to retail release...
 

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Its funny AMD Phenom 1 had the TLB bug and everyone lost their minds.
 

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Its funny AMD Phenom 1 had the TLB bug and everyone lost their minds.
Issues like this are common, the problem with the TLB bug was that the fix had a very notable affect on performance. Plus, AMD knew about the issue before releasing the processors(it was in the earlier released Opterons based on the same core, and the knew about it before the Phenom's release). So the performance hit, and the fact that AMD knew about it before releasing the processors, and only issued the fix after the reviews on the processors were done, making the processors look faster than they really were, is why people were harsh on AMD.
 
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I'm gonna try OCing my locked Skylake i5 chip after updating my board's BIOS & see how it goes. Will update on this thread whether the freeze bug can be replicated or not.
 
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I'm gonna try OCing my locked Skylake i5 chip after updating my board's BIOS & see how it goes. Will update on this thread whether the freeze bug can be replicated or not.
Are there any Skylake i5's with hyperthreading?

Bug won't happen without that.
 
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