Intel's 18A Node Outperforms TSMC N2 and Samsung SF2 in 2 nm Performance Class

[AleksandarK]

Intel's 18A node isn't all about yields and density (which are still very important factors) but also performance. According to Taiwanese media 3C News, citing TechInsights research and calculations, the new leader of node performance is Intel 18A. On a custom scale used by TechInsights, Intel 18A gets a 2.53 score, while the performance score of TSMC N2 is 2.27, and the performance score of Samsung SF2 is 2.19. This is all among two nm-class nodes, where Intel leads the category. Being the first node with a Backside Power Delivery Network (BSPDN), it will appear in the Panther Lake CPUs in late 2025 for testing and early 2026 for shipments. This new power architecture boosts layout efficiency and component utilization by 5-10%, lowers interconnect resistance, and enhances ISO power performance by up to 4%, thanks to a significant drop in intrinsic resistance versus traditional front‑end power routing. Relative to its predecessor, Intel 3, the 18A process delivers a 15% improvement in performance per watt and packs 30% more transistors into the same area.

Featuring RibbonFET design, it has entered risk production. According to Intel, "This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025." When it comes to other aspects like SRAM density, high‑performance SRAM cells shrank from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A, while high‑density cells contracted to 0.021 µm², reflecting scaling factors of 0.77 and 0.88 respectively and defying previous assumptions that SRAM scaling had plateaued. Intel's innovative "around‑the‑array" PowerVia approach addresses voltage drops and interference by routing power vias to I/O, control, and decoder circuits, freeing up the bit‑cell area from frontal power supplies. The result is a 38.1 Mbit/mm² macro bit density, positioning Intel to rival TSMC's N2. All this, combined with BSPDN, is shaping up a powerful node. We can't wait to get our hands on some 18A silicon in the future and run it through our labs for testing.



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[AleksandarK]

BTW I trust TechInisghts' scale as these guys are full professional engineers and analysts.

 

[ncrs]

I remember the hype surrounding Intel 20A and that didn't turn out well.
Personally I'll only believe such claims when mass manufactured products are benchmarked by independent third parties.

 

[tfp]

I think that the backside power delivery helps with the scaling vs running the power between the transiters wasting space.

 

[MxPhenom 216]

I think that the backside power delivery helps with the scaling vs running the power between the transiters wasting space.

Hmmm,

What layer do you think the standard cells sit on, vs what layer is the power routed in at compared to backside?

 

[tfp]

Hmmm,

What layer do you think the standard cells sit on, vs what layer is the power routed in at compared to backside?

I remember the front side diagrams showing the power "rails" going all they way through the chip vs not on back side.

Looking again it seems like the "size" of the signal wires is smaller and not competing for space? I might have miss understood/remembered the diagram and it doesn't impact the transistor size. Seems like only if the signal or power wire placement was impacting transistor placement that it could help with density.

my googling failed to find the similar article here, and I'm sure there has too be one.

Backside Power Delivery Gears Up For 2nm Devices

But this novel approach to optimizing logic performance depends on advancing lithography, etching, polishing, and bonding processes.

semiengineering.com

 

[Wirko]

I remember the front side diagrams showing the power "rails" going all they way through the chip vs not on back side.

Looking again it seems like the "size" of the signal wires is smaller and not competing for space? I might have miss understood/remembered the diagram and it doesn't impact the transistor size. Seems like only if the signal or power wire placement was impacting transistor placement that it could help with density.

View attachment 395053

my googling failed to find the similar article here, and I'm sure there has too be one.

Backside Power Delivery Gears Up For 2nm Devices

But this novel approach to optimizing logic performance depends on advancing lithography, etching, polishing, and bonding processes.

semiengineering.com

All wires on one layer are of the same size (cross-section) and all run in the same direction. None of the diagrams and microscope images I've seen suggests otherwise. When looking at diagrams like these, keep in mind that wires on each layer are perpendicular to wires on the layer just below it, so the diagrams show alternating cross-sections and lengthwise sections.

Some layers are probably more overcrowded with both signal and power wires than other layers, and those should benefit most from BSPDN.

It is unclear how dense these power vias are - can every SRAM cell have its own pair of vias, for example?

 

[Squared]

Even in recent times, Intel's nodes have remained somewhat competitive with TSMC's nodes in terms of performance. The struggle has been density. But more performance is still good.

 

[LittleBro]

Will believe when I see it, lol.

Looking forward to Intel releasing anything on their 18A in 1H26.

 

[alwayssts]

BTW I trust TechInisghts' scale as these guys are full professional engineers and analysts.

So do I, but I also think not figuring in TSMC/Samsung's BSPD (A16/2z) processes is slightly disingenuous; where BSPD improves area 10-20% and/or performance by 5-10%, which would even things out.
And in reality may yield (especially for outside customers) in a similar time-frame. Just using the '2nm' nodes because of the name is a little odd. Why not 20A for Intel, then? A16/2z is just 2nm w/BSPD.

How much do you think their rating would change from the addition of a BSPD network for TSMC/Samsung? Now add, for instance, TSMC's density improvement (options) vs Intel. It should equal out.
Samsung perhaps slightly behind, but they're also generally a value contender, so it makes sense. They'll also likely be close-enough for similar designs to make sense, and may gain most from BSPD.

With TSMC you could build toward area (N2), or toward increasingly higher performance/area/power (N2P/X) and then even better at higher cost (A16); similar with Samsung (eventually).
With Intel it would appear you would be stuck with a very particular parameter, catered toward high performance but not factoring in optimal cost/area/power for a product.

Hence I think this is a fairly odd way to judge things, as not all designs will fit perfectly within the tuning of 18A, nor will/would they have an optimized cost (for companies nor their clients).
TSMC/Samsung do have those options and/or will.
I would feel much better about article if it relayed the differences between 18A, A16, and N2Z for performance; or 18A, N2 (which is built for density), and 2N (which is in-between N3P and N2) for cost/power/density.

It's fair to give something a rating based on performance (ie clockspeed), as that relative capability is important, but then one should also do it for optimized area/power consumption (which they have not).
Especially when comparing the base nodes from the companies that are not Intel, all of which generally first focus on density/low power rather than performance. Hence this is slightly to highly misleading.

IOW, cool; they can run a BSPD chip at 1.2v+, where-as N2B is denser but isn't aimed toward that; probably ~1-1.05v. Probably similar for Samsung. That doesn't make 18A ~15% better, as this implies.
Also, almost nobody (outside of Apple) actually is using N2B. They will use N2P (~1.15v) or n2x (1.2v+) and/or A16 when available and feasible (especially in cost) versus N3(E/)P (and perhaps Samsung base 2nm).

If companies are considering using 18A, they would likely also consider A16 for the advantages of BSPD...but even then TSMC may cater designs toward different mixtures of density/performance.
Considering the cost, many may not, and instead opt for something like N2X (as AMD appears to be doing; high perf [perhaps similar to Intel] but similar/slightly less density and/or similar/worse power consumption).

This article is very nuanced, and kind of comparing apples to oranges imho, and comes across trying to put Intel in the best light possible using a very particular metric and comparison(s).

Even in recent times, Intel's nodes have remained somewhat competitive with TSMC's nodes in terms of performance. The struggle has been density. But more performance is still good.

Bingo. This guy gets it.

 

[KLMR]

ROFL.

 

[Visible Noise]

Hmmm,

What layer do you think the standard cells sit on, vs what layer is the power routed in at compared to backside?

I believe I read Intel is putting M1 and M2 on the backside. Couldn’t tell you where I read that though.

 

[tfp]

All wires on one layer are of the same size (cross-section) and all run in the same direction. None of the diagrams and microscope images I've seen suggests otherwise. When looking at diagrams like these, keep in mind that wires on each layer are perpendicular to wires on the layer just below it, so the diagrams show alternating cross-sections and lengthwise sections.

Some layers are probably more overcrowded with both signal and power wires than other layers, and those should benefit most from BSPDN.

It is unclear how dense these power vias are - can every SRAM cell have its own pair of vias, for example?

Thanks for the explanation Wirko!

 

[Marcus L]

Backside Power Delivery

 

[MxPhenom 216]

I believe I read Intel is putting M1 and M2 on the backside. Couldn’t tell you where I read that though.

The way I have understood it is that the backside is all power routing with the standard cells (active layers, poly, wells) sandwich inbetween with all the signal routing on the other side. I'm not sure how they are setting up the metal layers between the two sides tho.

This is very different than how current power networks are done. Currently the standard approach is basically piping power in fron the highest metal layer with VIAs piping the power down to M0 where standard cells power rails sit. All on the same side. So this removes area for standard cells and signal/clock routing.

 

[phints]

Here we go again with Intel lithography propaganda. They haven't been at the top of their process gaming in like a decade. If they release desktop and laptop CPUs that use 18A soon (before TSMC beats them) say by late 2026 it'll be great but who knows what's coming. Their competition isn't resting either.

 

[Squared]

So do I, but I also think not figuring in TSMC/Samsung's BSPD (A16/2z) processes is slightly disingenuous; where BSPD improves area 10-20% and/or performance by 5-10%, which would even things out.
And in reality may yield (especially for outside customers) in a similar time-frame. Just using the '2nm' nodes because of the name is a little odd. Why not 20A for Intel, then? A16/2z is just 2nm w/BSPD.

TSMC has backside power delivery slated for A16, which according to TSMC and Intel roadmaps will land around the same time as Intel 14A*. TSMC might ramp up faster and produce a greater volume, but if the first Intel 18A products are released this year (as promised) and feature backside power delivery (which Intel has not promised) and the rest of the roadmap is true, Intel will have had backside power delivery for about a year before TSMC.

*Intel's roadmap also puts 18A in 2024. It just entered risk production and I believe the current year is 2025. TSMC's roadmap has N3E in 2024, and Apple M4 chips on N3E did reach consumers that year. So TSMC's roadmap uses consumer-reaching dates and Intel's uses another metric which is perhaps 1 year before consumer release.

 

[truthsayer]

Panther Lake, 18A's lead product is a low volume, anemic ~110nm 4P+8E SOC, reading between the lines Intel is basically in the same position as with Tiger Lake for 10nm.

Intel 10 had similar density vs TSMC 7nm, and was ahead in technology (cobalt interconnect), density and technology were never Intel's problem.

TSMC is "conservative" in terms of density scaling and technology but they execute relentlessly. While their competitors (Samsung, Intel) are languishing behind, trying to "turn everything around" by being first on new technologies, TSMC had already progressed through multiple node generations/refinements, and had pumped out millions of wafers.

 

[Visible Noise]

Here we go again with Intel lithography propaganda. They haven't been at the top of their process gaming in like a decade. If they release desktop and laptop CPUs that use 18A soon (before TSMC beats them) say by late 2026 it'll be great but who knows what's coming. Their competition isn't resting either.

Did you read the article. Where does it say this info came from Intel? As a matter of fact it says just the opposite.

Hello Knee, meet Jerk.

 

[NoLoihi]

I think some people’s cautions on here are very valid (I don’t think all people’s are .) Overhyping won’t do Intel any favors, reality will come and set things straight, disappointments may be had. From the article (which I haven’t read yet) it can probably be gathered that whether or not 18A will be the sole leader, it surely won’t be utter failure, at least in performance. (Yields will dictate price.)
I’m glad for every bit of manufacturing Intel can bring back in house, it needs all the profit it can gain.

a low volume, anemic ~110nm 4P+8E SOC

Those are times of excess, when 4P+8E (better than Skymont) are seen as anemic.

 

[mechtech]

If so that's good news.

I guess the question I have then is why is Intel subbing so much fab work to TSMC?

 

[Tek-Check]

Intel's roadmap also puts 18A in 2024. It just entered risk production and I believe the current year is 2025. TSMC's roadmap has N3E in 2024, and Apple M4 chips on N3E did reach consumers that year. So TSMC's roadmap uses consumer-reaching dates and Intel's uses another metric which is perhaps 1 year before consumer release.

Also, "5 nodes in 4 years" has been the most meaningless and stupid narrative ever. The reality has shown that such propaganda pitched to tech media is not reflected in what's happening on the ground. Intel has gradually and literally lost market share with all those nodes in every single segment of PC and data center industries. The loss in desktop has accelerated in recent quarters more than before, and in data center AMD and ARM designs are going to reach around 50% of share within one year, if not sooner.

In addition, Panther Lake might have one or two showcase laptops by December 31, just like they did with Meteor Lake, but almost nobody in the world will be able to buy it in any meaningful quantities before mid Q1 2026.

 

[Visible Noise]

If so that's good news.

I guess the question I have then is why is Intel subbing so much fab work to TSMC?

Time to market. What TSMC is manufacturing now was designed years ago.

BTW, Intel has fabbed chips at TSMC for over three decades.

 

[Tek-Check]

Even in recent times, Intel's nodes have remained somewhat competitive with TSMC's nodes in terms of performance. The struggle has been density. But more performance is still good.

If those nodes remained somewhat competitive, why chip designer companies do not produce their leading chips with Intel Foundry, a branch of business that has experienced heavy, multi-billion losses, quarter after quarter after quarter? Surely, Apple, Nvidia, Qualcomm, MediaTek, AMD and others could ask Intel to etch their leading chips, no?

Do they trust Intel Foundry to deliver on what they need? The simple answer is no. And that's the key problem with Intel Foundry business. Intel has had a fundamental conflict of interest between branches of their business. Intel Foundry is yet to produce a leading chip for non-Intel entity that is better than Intel own chips.

TSMC doesn't have this issue as they are simply the leading global foundry without such conflict of interest.

Intel has fabbed chips at TSMC for over three decades

Yes, but they haven't outsourced entire generations of front line products, such as Lunar Lake. They were forced to do this as their own nodes were crappy at that time. TSMC has a better product and even the US government asked them to help save Intel Foundry from further bleeding.

 

[Squared]

In addition, Panther Lake might have one or two showcase laptops by December 31, just like they did with Meteor Lake, but almost nobody in the world will be able to buy it in any meaningful quantities before mid Q1 2026.

AMD Phoenix came out earlier in the same year as Meteor Lake. AMD said Phoenix was launched and for months I couldn't find Phoenix laptops, just the Asus ROG Ally. In December that year Intel "launched" Meteor Lake and I think two weeks later it was "released" and I found store listings of 4 different Meteor Lake laptops which all remained mostly in stock for the rest of December. Within a few months many more laptops were released. It was late to market especially compared to Phoenix but the messaging was much better than with Phoenix and availability went from not released to widely available in several months less time than Phoenix. I found people online lamenting what I saw: nobody could find Phoenix laptops for months, yet once Meteor Lake was released every enthusiast who tried to buy a Meteor Lake laptop had one within days.

If those nodes remained somewhat competitive, why chip designer companies do not produce their leading chips with Intel Foundry, a branch of business that has experienced heavy, multi-billion losses, quarter after quarter after quarter? Surely, Apple, Nvidia, Qualcomm, MediaTek, AMD and others could ask Intel to etch their leading chips, no?

When I said, "Intel's nodes have remained somewhat competitive with TSMC's nodes in terms of performance," I was responding to the article, "Intel's 18A node isn't all about yields and density." I was literally throwing water on the implication that 18A is better than N2 because it has better "performance". Nodes can tend toward transistor density or transistor performance, with either being a viable path to high-performance chips. Apple's chips favor high-density nodes as they have low frequency but a lot of transistors to deliver more instructions per clock cycle. Intel's chips favor high-performance transistors which can reach high clock speeds. This is probably a lot of why Arrow Lake on desktop has lower gaming performance than Raptor Lake; the TSMC N3B node is density-optimized and is limiting the clock speed of Arrow Lake. AMD had a similar problem when trying to build APUs in the early days: going from Global Foundries 32nm with Piledriver to Global Foundries 28nm Steam Roller AMD saw a nice performance gain in the iGPU and good laptop performance, but a regression in desktop CPU performance because the 28nm node had been specially designed to achieve a balance between CPU and GPU needs, and this hurt the CPU. It's probably also why Alchemist and Battlemage are made by TSMC; GPUs benefit more from density. Smartphone SoCs and GPUs and many server CPUs favor density over performance, and this makes it hard for Intel to sell its performance-optimized nodes to most customers.