Monday, April 14th 2025
Intel's 18A Node Outperforms TSMC N2 and Samsung SF2 in 2 nm Performance Class
Intel's 18A node isn't all about yields and density (which are still very important factors) but also performance. According to Taiwanese media 3C News, citing TechInsights research and calculations, the new leader of node performance is Intel 18A. On a custom scale used by TechInsights, Intel 18A gets a 2.53 score, while the performance score of TSMC N2 is 2.27, and the performance score of Samsung SF2 is 2.19. This is all among two nm-class nodes, where Intel leads the category. Being the first node with a Backside Power Delivery Network (BSPDN), it will appear in the Panther Lake CPUs in late 2025 for testing and early 2026 for shipments. This new power architecture boosts layout efficiency and component utilization by 5-10%, lowers interconnect resistance, and enhances ISO power performance by up to 4%, thanks to a significant drop in intrinsic resistance versus traditional front‑end power routing. Relative to its predecessor, Intel 3, the 18A process delivers a 15% improvement in performance per watt and packs 30% more transistors into the same area.
Featuring RibbonFET design, it has entered risk production. According to Intel, "This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025." When it comes to other aspects like SRAM density, high‑performance SRAM cells shrank from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A, while high‑density cells contracted to 0.021 µm², reflecting scaling factors of 0.77 and 0.88 respectively and defying previous assumptions that SRAM scaling had plateaued. Intel's innovative "around‑the‑array" PowerVia approach addresses voltage drops and interference by routing power vias to I/O, control, and decoder circuits, freeing up the bit‑cell area from frontal power supplies. The result is a 38.1 Mbit/mm² macro bit density, positioning Intel to rival TSMC's N2. All this, combined with BSPDN, is shaping up a powerful node. We can't wait to get our hands on some 18A silicon in the future and run it through our labs for testing.
Source:
3C News
Featuring RibbonFET design, it has entered risk production. According to Intel, "This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025." When it comes to other aspects like SRAM density, high‑performance SRAM cells shrank from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A, while high‑density cells contracted to 0.021 µm², reflecting scaling factors of 0.77 and 0.88 respectively and defying previous assumptions that SRAM scaling had plateaued. Intel's innovative "around‑the‑array" PowerVia approach addresses voltage drops and interference by routing power vias to I/O, control, and decoder circuits, freeing up the bit‑cell area from frontal power supplies. The result is a 38.1 Mbit/mm² macro bit density, positioning Intel to rival TSMC's N2. All this, combined with BSPDN, is shaping up a powerful node. We can't wait to get our hands on some 18A silicon in the future and run it through our labs for testing.
36 Comments on Intel's 18A Node Outperforms TSMC N2 and Samsung SF2 in 2 nm Performance Class
Personally I'll only believe such claims when mass manufactured products are benchmarked by independent third parties.
What layer do you think the standard cells sit on, vs what layer is the power routed in at compared to backside?
Looking again it seems like the "size" of the signal wires is smaller and not competing for space? I might have miss understood/remembered the diagram and it doesn't impact the transistor size. Seems like only if the signal or power wire placement was impacting transistor placement that it could help with density.
my googling failed to find the similar article here, and I'm sure there has too be one.
semiengineering.com/backside-power-delivery-gears-up-for-2nm-devices/
Some layers are probably more overcrowded with both signal and power wires than other layers, and those should benefit most from BSPDN.
It is unclear how dense these power vias are - can every SRAM cell have its own pair of vias, for example?
Looking forward to Intel releasing anything on their 18A in 1H26.
And in reality may yield (especially for outside customers) in a similar time-frame. Just using the '2nm' nodes because of the name is a little odd. Why not 20A for Intel, then? A16/2z is just 2nm w/BSPD.
How much do you think their rating would change from the addition of a BSPD network for TSMC/Samsung? Now add, for instance, TSMC's density improvement (options) vs Intel. It should equal out.
Samsung perhaps slightly behind, but they're also generally a value contender, so it makes sense. They'll also likely be close-enough for similar designs to make sense, and may gain most from BSPD.
With TSMC you could build toward area (N2), or toward increasingly higher performance/area/power (N2P/X) and then even better at higher cost (A16); similar with Samsung (eventually).
With Intel it would appear you would be stuck with a very particular parameter, catered toward high performance but not factoring in optimal cost/area/power for a product.
Hence I think this is a fairly odd way to judge things, as not all designs will fit perfectly within the tuning of 18A, nor will/would they have an optimized cost (for companies nor their clients).
TSMC/Samsung do have those options and/or will.
I would feel much better about article if it relayed the differences between 18A, A16, and N2Z for performance; or 18A, N2 (which is built for density), and 2N (which is in-between N3P and N2) for cost/power/density.
It's fair to give something a rating based on performance (ie clockspeed), as that relative capability is important, but then one should also do it for optimized area/power consumption (which they have not).
Especially when comparing the base nodes from the companies that are not Intel, all of which generally first focus on density/low power rather than performance. Hence this is slightly to highly misleading.
IOW, cool; they can run a BSPD chip at 1.2v+, where-as N2B is denser but isn't aimed toward that; probably ~1-1.05v. Probably similar for Samsung. That doesn't make 18A ~15% better, as this implies.
Also, almost nobody (outside of Apple) actually is using N2B. They will use N2P (~1.15v) or n2x (1.2v+) and/or A16 when available and feasible (especially in cost) versus N3(E/)P (and perhaps Samsung base 2nm).
If companies are considering using 18A, they would likely also consider A16 for the advantages of BSPD...but even then TSMC may cater designs toward different mixtures of density/performance.
Considering the cost, many may not, and instead opt for something like N2X (as AMD appears to be doing; high perf [perhaps similar to Intel] but similar/slightly less density and/or similar/worse power consumption).
This article is very nuanced, and kind of comparing apples to oranges imho, and comes across trying to put Intel in the best light possible using a very particular metric and comparison(s).Bingo. This guy gets it.
This is very different than how current power networks are done. Currently the standard approach is basically piping power in fron the highest metal layer with VIAs piping the power down to M0 where standard cells power rails sit. All on the same side. So this removes area for standard cells and signal/clock routing.
*Intel's roadmap also puts 18A in 2024. It just entered risk production and I believe the current year is 2025. TSMC's roadmap has N3E in 2024, and Apple M4 chips on N3E did reach consumers that year. So TSMC's roadmap uses consumer-reaching dates and Intel's uses another metric which is perhaps 1 year before consumer release.
Intel 10 had similar density vs TSMC 7nm, and was ahead in technology (cobalt interconnect), density and technology were never Intel's problem.
TSMC is "conservative" in terms of density scaling and technology but they execute relentlessly. While their competitors (Samsung, Intel) are languishing behind, trying to "turn everything around" by being first on new technologies, TSMC had already progressed through multiple node generations/refinements, and had pumped out millions of wafers.
Hello Knee, meet Jerk.
I’m glad for every bit of manufacturing Intel can bring back in house, it needs all the profit it can gain.Those are times of excess, when 4P+8E (better than Skymont) are seen as anemic.
I guess the question I have then is why is Intel subbing so much fab work to TSMC?
In addition, Panther Lake might have one or two showcase laptops by December 31, just like they did with Meteor Lake, but almost nobody in the world will be able to buy it in any meaningful quantities before mid Q1 2026.
BTW, Intel has fabbed chips at TSMC for over three decades.
Do they trust Intel Foundry to deliver on what they need? The simple answer is no. And that's the key problem with Intel Foundry business. Intel has had a fundamental conflict of interest between branches of their business. Intel Foundry is yet to produce a leading chip for non-Intel entity that is better than Intel own chips.
TSMC doesn't have this issue as they are simply the leading global foundry without such conflict of interest.Yes, but they haven't outsourced entire generations of front line products, such as Lunar Lake. They were forced to do this as their own nodes were crappy at that time. TSMC has a better product and even the US government asked them to help save Intel Foundry from further bleeding.