LPDDR6 LPCAMM2 Pictured and Detailed Courtesy of JEDEC

[TheLostSwede]

Yesterday we reported on DDR6 memory hitting new heights of performance and it looks like LPDDR6 will follow suit, at least based on details in a JEDEC presentation. LPDDR6 will just like LPDDR5 be available as solder down memory, but it will also be available in a new LPCAMM2 module. The bus speed of LPDDR5 on LPCAMM2 modules is expected to peak at 9.2 GT/s based on JEDEC specifications, but LPDDR6 will extend this to 14.4 GT/s or roughly a 50 percent increase. However, today the fastest and only LPCAMM2 modules on the retail market which are using LPDDR5X, comes in at 7.5 GT/s, which suggests that launch speeds of LPDDR6 will end up being quite far from the peak speeds.

There will be some other interesting changes to LPDDR6 CAMM2 modules as there will be a move from 128-bit per module to 192-bit per module and each channel will go from 32-bits to 48-bits. Part of the reason for this is that LPDDR6 is moving to a 24-bit channel width, consisting of two 12-bit sub channels, as mentioned in yesterday's news post. This might seem odd at first, but in reality is fairly simple, LPDDR6 will have native ECC (Error Correction Code) or EDC (Error Detection Code) support, but it's currently not entirely clear how this will be implemented on a system level. JEDEC is also looking at developing a screwless solution for the CAMM2 and LPCAMM2 memory modules, but at the moment there's no clear solution in sight. We might also get to see LPDDR6 via LPCAMM2 modules on the desktop, although the presentation only mentions CAMM2 for the desktop, something we've already seen that MSI is working on.



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[LabRat 891]

Can't say I disagree with the purpose of LPCAMM.



Shorter, simplified traces means better signal integrity and lower physical latency.

The 'jumble' of non-intercompatible standards is a bit concerning, however.

 

[TheLostSwede]

Can't say I disagree with the purpose of LPCAMM.

View attachment 348610

Shorter, simplified traces means better signal integrity and lower physical latency.

The 'jumble' of non-intercompatible standards is a bit concerning, however.

But would you be willing to step down to a single memory module in your PC?
There are apparently some issues with stacking the SC CAMM2 modules.
It might be possible to put one CAMM2/LPCAMM2 on each side of a motherboard though, but I haven't seen this proposed anywhere.

 

[bonehead123]

As long as it's better, faster AND cheaper, bring it, like, yesterday

JEDEC's gonna have to get the mobo makers on board (no pun intended) to make the concept into a widely accepted and affordable standard though (just like the rear connector thing).

Otherwise, m.E.h.....

But would you be willing to step down to a single memory module in your PC?

If the capacity is large enough (128GB or more), then yes I would....

 

[Pepamami]

I once tried to explain why you don't insert memory in A1 and B1 slots, and go to the last one, A2 and B2. By explaining all these interference, SI (signal integrity) stubs, On-Die Termination, Open Circuit and etc, things.

But people called me a moron xd

 

[Mawkzin]

But would you be willing to step down to a single memory module in your PC?
There are apparently some issues with stacking the SC CAMM2 modules.
It might be possible to put one CAMM2/LPCAMM2 on each side of a motherboard though, but I haven't seen this proposed anywhere.

Isn't the standart to use only on module with the full bus? If the cpu is 128 bit wide bus you'll use the 128bit module and if the cpu is 64 you'll use the 64bit module.

 

[Pepamami]

But would you be willing to step down to a single memory module in your PC?

If it will be 128bit and Dual-Rank. Then it does not matter, since people already buy memory in Kits. But if it will be Single-Rank only, then hell no, coz when u have 4 lines, at least u can fix dual-rank.

 

[TheLostSwede]

Isn't the standart to use only on module with the full bus? If the cpu is 128 bit wide bus you'll use the 128bit module and if the cpu is 64 you'll use the 64bit module.

What do you use today? Two 64-bit modules for a 128-bit bus, no?

If it will be 128bit and Dual-Rank. Then it does not matter, since people already buy memory in Kits. But if it will be Single-Rank only, then hell no, coz when u have 4 lines, at least u can fix dual-rank.

It doesn't have to be. The DXXX type is meant for stacking, which means each CAMM2 is only single channel and you need two of them to make it dual channel.

As announced earlier this year, JESD318 CAMM2 supports stackable CAMM2s: dual-channel (DC) and single-channel (SC). By splitting the dual-channel CAMM2 connector lengthwise into two single-channel CAMM2 connectors, each connector half can elevate the CAMM2 to a different level. The first connector half supports one DDR5 memory channel at 2.85mm height while the second half supports a different DDR5 memory channel at 7.5mm height. Or, the entire CAMM2 connector can be used with a dual-channel CAMM2. This scalability from single-channel and dual-channel configurations to future multi-channel setups promises a significant boost in memory capacity.

JEDEC Publishes New CAMM2 Memory Module Standard | JEDEC

www.jedec.org

 

[Wirko]

As long as it's better, faster AND cheaper, bring it, like, yesterday

Knowing that most things were cheaper yesterday than they are today, I cannot not agree.

@TheLostSwede The CAMM modules have 8, 16 or 32 chips. What about ECC, which requires 25% more chips? It doesn't appear there is any space reserved for them.

 

[Mawkzin]

What do you use today? Two 64-bit modules for a 128-bit bus, no?

I was talking about the CAMM standart. When Dell announced the standart, the CAMM where designed to be 128bit for module, you would use only one module with what you need.
When JEDEC announced the CAMM2 they talked about 128 and 64 bit modules.

It seems that the LPDDR6 will be moving to 192 bit bus, when they're schedule to hit the market?

 

[Pepamami]

It doesn't have to be. The DXXX type is meant for stacking, which means each CAMM2 only single channel and you need two of them to make it dual channel.

technically DDR5 use 32bit channels. So I dont see any problems to have one 128bit module. with 32+32+32+32 bits setups. The only thing I am missing - Dual Rank.
like JESD318 CAMM2 is stackable, I don't see a problem to have 1 module, that is already stacked.

 

[Wirko]

technically DDR5 use 32bit channels. So I dont see any problems to have one 128bit module. with 32+32+32+32 bits setups. The only thing I am missing - Dual Rank.
like JESD318 CAMM2 is stackable, I don't see a problem to have 1 module, that is already stacked.

The Bxxx modules have as many as 32 chips (16 on each side) that together make a 128-bit data bus. I think this can't be single rank.

(And besides that, each subchannel has its own set of ranks, so "single" means four in total anyway.)

 

[Pepamami]

The Bxxx modules have as many as 32 chips (16 on each side) that together make a 128-bit data bus. I think this can't be single rank.

(And besides that, each subchannel has its own set of ranks, so "single" means four in total anyway.)

ye, making build-in rank interleaving is a nice idea. The whole idea of dual-rank is to be able to work with one side of memory, while other is "charging"

 

[TheLostSwede]

@TheLostSwede The CAMM modules have 8, 16 or 32 chips. What about ECC, which requires 25% more chips? It doesn't appear there is any space reserved for them.

I guess you need to re-read the news post and you'll get it, especially the second paragraph.

I was talking about the CAMM standart. When Dell announced the standart, the CAMM where designed to be 128bit for module, you would use only one module with what you need.
When JEDEC announced the CAMM2 they talked about 128 and 64 bit modules.

It seems that the LPDDR6 will be moving to 192 bit bus, when they're schedule to hit the market?

Sorry, but your original post was a bit hard to decode. Yes, Dell had only designed it for a 128-bit interface AFAIK.

As for when this will hit the market, who knows, the DDR6 specs aren't expected to be done until mid 2025, no mention of LPDDR6, but the LP type memory appears to be half a cycle ahead of DDR, so maybe the spec will be done this year, so availability 2025-2026?

technically DDR5 use 32bit channels. So I dont see any problems to have one 128bit module. with 32+32+32+32 bits setups. The only thing I am missing - Dual Rank.
like JESD318 CAMM2 is stackable, I don't see a problem to have 1 module, that is already stacked.

Look at the picture I posted. Type A, B and C are all 128-bit, only type D is 64-bit per module.
Also, DDR6/LPDDR6 will be 48-bit, not 32-bit.

 

[mrdumbasspremium]

Can't say I disagree with the purpose of LPCAMM.

View attachment 348610

Shorter, simplified traces means better signal integrity and lower physical latency.

The 'jumble' of non-intercompatible standards is a bit concerning, however.

1.The purpose is absolute garbage, more speeds (excluding arch/memory signaling) at the cost of system expandability ruined. Meaning customers have to pay more in the end while the company makes higher profits, not fun.

2. Shorter traces can be accomplished off our current desktop DCP's by rotating the CPU that way the memory controller is in line with the DPC's. In the end if you tried both and tried your absolute best to make the wires shorter by moving things around we are talking about a difference that is damn near 5-7.5% at BEST case (which is god damn useless)

3. They make this confusing that way when normal people read this they have little to no clue what's going on, It's literally just input and output through a wire mainly concerning a PCB with a bunch of silicon DRAM chips on it and another peice of silicon with the entire CPU, including the IMC.

 

[Zareek]

But would you be willing to step down to a single memory module in your PC?
There are apparently some issues with stacking the SC CAMM2 modules.
It might be possible to put one CAMM2/LPCAMM2 on each side of a motherboard though, but I haven't seen this proposed anywhere.

I would be happy to install one memory module on my PC, I recently realized that I never populate two of the four DIMM slots anyway. This also could help with some of the memory clearance issues that some large air coolers cause. I love the idea of a module on each side of the board, especially if that means more memory channels for feeding an APU for instance.

 

[Pepamami]

I would be happy to install one memory module on my PC, I recently realized that I never populate two of the four DIMM slots anyway. This also could help with some of the memory clearance issues that some large air coolers cause. I love the idea of a module on each side of the board, especially if that means more memory channels for feeding an APU for instance.

u need 4 modules if u have Single Rank modules and want Dual Rank system, but in other cases 4 slots feels like some legacy stuff from OLD pcs.

 

[remixedcat]

How can anyone hate this new memory standard I think it's got the best of both worlds, speed and upgradeability/replaceability... so now we can do away w soldered ram... this is also I think thinner so you can still have ram replace/upgrades on a very thin n light tablet or laptop. but how much thinner than an average sodimm?

also if you have this on desktops you can have more room for a beefier cpu cooler too

 

[Dr. Dro]

How can anyone hate this new memory standard I think it's got the best of both worlds, speed and upgradeability/replaceability... so now we can do away w soldered ram... this is also I think thinner so you can still have ram replace/upgrades on a very thin n light tablet or laptop. but how much thinner than an average sodimm?

It's as @mrdumbasspremium explained. He didn't leave much unsaid. I'd also argue that it's probably undesirable to have a thin and light laptop with upgradable memory, might as well go all the way if you're subjecting yourself to that.

In this scenario, you've already hosed yourself out of having a good system by buying thin and light (it's inevitably throttle happy, has a tiny battery that doesn't last, it's thermally limited so it never performs to its fullest extent and the machine gets out of the factory almost obsolete, since it's designed to be replaced within a generational cycle anyway), so might as well enjoy the security benefits of a secured-core PC-compliant system with soldered RAM.

It's unrelated nonsense, but this single-module back and forth somehow reminded me of AMD's old ganged memory mode, in which the memory controller operated both the two 64-bit channels as a single, fat 128-bit channel. The idea at the time is that by doing this, you'd obtain better bandwidth utilization figures in single-threaded workloads.

I guess it shouldn't be surprising that in the end JEDEC adopted the extreme opposite with the pseudo-quad channel offered by DDR5 (which breaks each channel into two independent 32-bit subchannels).

 

[remixedcat]

I was only using the thin n light as an example where it would also be good.. not my personal example....

 

[Dr. Dro]

I was only using the thin n light as an example where it would also be good.. not my personal example....

I know, my text also should not be interpreted as an accusation, but a hypothetical

 

[remixedcat]

I know, my text also should not be interpreted as an accusation, but a hypothetical

Ok... but yeah this standard is still awesome tho

 

[Zareek]

u need 4 modules if u have Single Rank modules and want Dual Rank system, but in other cases 4 slots feels like some legacy stuff from OLD pcs.

Yeah, I stopped fussing over the small details years ago. I go for the sweet spot, set it and forget it.

 

[Noyand]

1.The purpose is absolute garbage, more speeds (excluding arch/memory signaling) at the cost of system expandability ruined. Meaning customers have to pay more in the end while the company makes higher profits, not fun.

2. Shorter traces can be accomplished off our current desktop DCP's by rotating the CPU that way the memory controller is in line with the DPC's. In the end if you tried both and tried your absolute best to make the wires shorter by moving things around we are talking about a difference that is damn near 5-7.5% at BEST case (which is god damn useless)

3. They make this confusing that way when normal people read this they have little to no clue what's going on, It's literally just input and output through a wire mainly concerning a PCB with a bunch of silicon DRAM chips on it and another peice of silicon with the entire CPU, including the IMC.

From what I understand, Jedec is looking at things beyond the DDR5/DDR6 era. SODIMM is already having trouble reaching 6000mhz, and it sounds like DIMM might reach its limits in a few generations. (Even G-skill so-dimms are either strictly sticking to Jedec speed and timings or are even slower.) They didn't limit the mention to "gaming PC" but to servers as well. Time will tell if I was wrong, but I don't think that it's about "Extreme overclocking", but really about avoiding stagnation in-memory performance because DDR7/8/9 DIMMs might not be able to extract all the potential of the new standards.

Even on the server space, there's going to be a point where people won't want to deal with 64 channels of memory if the sticks can't get faster

For the desktop, from what I've gathered, people who want fast memory are sticking to a kit of two sticks anyway, since four sticks might not even be stable at XMP ever since we've entered the DDR5 era. Even quad channel 6400mhzCL32 seems hard to pull off... I wonder how many people on TPU are running with four sticks on their personal machine. Especially when the capacity of a single stick seems to quadruple every generation

What bothers me is that the form factor requires more horizontal space... by a big margin