Rumor: AMD Rembrandt APUs to Feature Zen3+, RDNA2 Architectures - Up to 12 CUs

[Turmania]

I'm really shocked how AMD did not deliver consumers an integrated gpu even if its vega with their new cpu gen. That would finally knock out Intel. That would have opened up a lot more market and market share for them.

 

[Chrispy_]

12CU of RDNA2 should be roughly twice the speed of Vega8, even more if it's on a DDR5 platform.

The bad news is that it's a LOOOOONG way away and Intel's IGPs are improving much faster than AMD's IGPs are improving; It may be too little, too late.

 

[WhitetailAni]

I don't like Apple but least M1 name is simple, M and 1. Intel has many lakes and wells and those get messy, NVidia and AMD keeps attaching their product with (influential)people and places, at some point it all looks like marketing ploy.

Waiting for Nintendo to release the New Nintendo 23DSi XL Lite.

Back to Zen3+, will it be AM4, AM5, or both? Given that AMD's using a chiplet design, in theory it wouldn't be too hard for them to make separate DDR4 and DDR5 I/O dies.

 

[xChoice]

Finally (hopefully) no more vega crap -_-!!!

 

[lexluthermiester]

Finally (hopefully) no more vega crap -_-!!!

I think it can be said with confidence that we're passed it.

 

[Wirko]

Back to Zen3+, will it be AM4, AM5, or both? Given that AMD's using a chiplet design, in theory it wouldn't be too hard for them to make separate DDR4 and DDR5 I/O dies.

Those who know won't tell. I don't know, therefore I tell.

By the time Alder Lake arrives, AMD needs to have something new ready too. Without unlimited resources, they can't have a new socket, new chipset, new Zen, and new DDR and new PCIe controllers, all at the same time and properly tested. Without really unlimited resources, they can't steal 5nm wafer starts from under Apple's nose. So they decide on AM5 and DDR5, but old Zen (refreshed), old process (refreshed) and old PCIe, which is a good fit for a monolithic APU. The graphics will benefit a lot from DDR5 bandwidth here.

It will be something of a disappointment to enthusiasts, but so will be Alder Lake, so there. AMD then has enough time to finish Zen 4 and PCIe 5, and debug DDR5.

Regarding DDR5, there's surprisingly little information about it half a year before supposed launch, and the available info points at high latencies. I think that the technology is difficult like hell to implement and the first generation of controllers (from AMD, Intel, whoever) and modules will come loaded with bugs, with poor compatibility, stability and latencies. And gears, oh, gears! But you've got to start somewhere, and it better be a midrange product than something aimed at the most demanding crowd.

 

[prtskg]

You guys think adding AMD's Infinity cache into their APU's would remedy the issue that they've been having since they first launched, memory bandwidth?

These will use DDR5, I think.