Tips to get 1T stable with overclock

[terminalinfinity]

I'm overclocking my RAM and keep coming across this site and its Ryzen articles from 1sumus, I'd figured I'd ask for help with my overclock here.

I have some Samsung B-die modules (K4A8G085WB-BCPB chips) that seem to be really good overclockers. I've reached the vaunted 3733 CL14 mark with stability (OCCT-4 hours and Memtest verified) and after learning that it's sometimes better to dial back memory controller voltage (VDDP I think?). I seemed stable at 3800 CL14 as well, but the temps passed 45 degrees C on the middle 2 DIMMs so I dialed it back. (I have 4 DIMMs) I may try again later after seeing if I can dial back some voltages and try lower resistances and lower temps.

The issue is, as soon as I tried to overclock anything I had to go to gear down mode rather than 1T, which worked on the stock XMP 3600 16-16-16-16-38 settings. I have found a few recommendations in guides, but haven't been able to get anything to work.

Gear down mode doesn't seem to be the worst from what I've read. more like a 1.5T than anything. However, I'd like to try to get it working and learn more about RAM timings in the process.

I was able to boot with gear down mode off with CAD strength to 60-20-20-24 and all the CAD bus timings set to 63, which was something I found as a recommendation on an OC guide on github. But it was totally unstable. The guide then just says to "Adjust setup times then drive strengths if unstable "
I tried moving some stuff around but that just made it more unstable/prone to blue screen.

I have two questions
1. Is there anything else I can try to get 1T stable or a pattern to how I should alter drive strengths/setup times in an attempt for stablity?
2. Should I try to reduce timings before attempting 1T or after?

Setup:
Ryzen 3600
MSI B550 Tomahawk
4X 8GB GSkill Trident DDR4 Samsung B-die (Stock XMP: DDR4-3600 16-16-16-16-38)

My current stable settings
DDR-3733 @ 14-16-16-16-40 (Not done tightening timings)
RAM Voltage: 1.5 volts
Mem VTT: 0.75
SOC voltage: 1.1

 

[dark2099]

Can you upload a picture of DRAM calc for us to see? For all the voltages, and other options that have a few options for being set, have you tried all the different ones?

 

[terminalinfinity]

Can you upload a picture of DRAM calc for us to see? For all the voltages, and other options that have a few options for being set, have you tried all the different ones?

I've messed with the voltages relating to the infinity fabric speed/memory controller, however I think Im at the pretty optimal points. Raising them seems to result in more instability, even in otherwise verified stable settings. For example it seems to like .900-.950 CLDO vddp. It bucks at 1 even though I should still have headroom. Less is more here it seems in regards to my stability.

Obviously being at 1.5 volts for the RAM itself Im at the limit for daily samsung B-die use so that alley is closed.

The DRAM calculator says CL14@3733 shouldn't even be possible on these dies, so I'm somewhat flying blind.

 

[dark2099]

I'm curious, for DRAM PCB Version, have you tried the A2 setting? SInce B-Dies are great for clocking, might get more compatible timings and options. I have some B-Dies, that I've use A2 on, and run only the settings from Main, didn't touch anything from Advanced, never did any stability testing, as I was simply trying to see where I got the best benchmark scores from.

 

[tabascosauz]

If you still have the Vdram headroom to do so (not much left past 1.5V daily, though), it's honestly better to keep Geardown on and forget about reaching pure 1T. I know the guide that you're referring to - memtesthelper, and it does suggest adjusting CADBUS until you can achieve stability, but I'm in the same shoes; I've sunk much more time than I should trying different CADBUS combinations and it simply doesn't work. Boot yes, POST yes, AIDA yes, nothing "stable" past that. It doesn't change anything that I can and can't already do without Geardown at stock CADBUS. I'm starting to think that with most things, only moar Vdram has the potential to eliminate Geardown.

The point with B-die is that everything scales with voltage. If the timings aren't as tight as they can possibly be, you're wasting your time with Geardown off. You're not flat on tRCD and tRP yet, those should be your priority. You could recoup that 0.5ns of Geardown latency with tRCD and tRP alone if you tighten them enough.

RDRDSCL and WRWRSCL should be at 4 maximum, shouldn't ever be a challenge for any IC. tRFC is way too damn high for anything that isn't at 2T command rate - 261-373 range for Bdie @ 3733. WTRL/S and WR are also looking wack, 4/12/12 at the very highest and work WTRS and WR down from there. RRDS/L and FAW looking decent.

VDDP is more a seat-of-the-pants thing. Also, use Zentimings to view everything useful in the same place https://zentimings.protonrom.com/

And don't think too negatively about Geardown. It allows you to run way higher than you otherwise would at 1T, and is a big boost to stability. Intel guys don't even have it, 1T or bust (2T).

 

[terminalinfinity]

I'm curious, for DRAM PCB Version, have you tried the A2 setting? SInce B-Dies are great for clocking, might get more compatible timings and options. I have some B-Dies, that I've use A2 on, and run only the settings from Main, didn't touch anything from Advanced, never did any stability testing, as I was simply trying to see where I got the best benchmark scores from.

Yup, those were the first I tried when I realized I had "A1" dies which weren't specifically listed. The manual calculations from the imported profile on Thaiphoon burner gave me the closest calculations to a working configuration

If you still have the Vdram headroom to do so (not much left past 1.5V daily, though), it's honestly better to keep Geardown on and forget about reaching pure 1T. I know the guide that you're referring to - memtesthelper, and it does suggest adjusting CADBUS until you can achieve stability, but I'm in the same shoes; I've sunk much more time than I should trying different CADBUS combinations and it simply doesn't work. Boot yes, POST yes, AIDA yes, nothing "stable" past that. It doesn't change anything that I can and can't already do without Geardown at stock CADBUS.

The point with B-die is that everything scales with voltage. If the timings aren't as tight as they can possibly be, you're wasting your time with Geardown off. You're not flat on tRCD and tRP yet, those should be your priority. You could recoup that 0.5ns of Geardown latency with tRCD and tRP alone if you tighten them enough.

RDRDSCL and WRWRSCL should be at 4 maximum, shouldn't ever be a challenge for any IC. tRFC is way too damn high for anything that isn't at 2T command rate - 261-373 range for Bdie @ 3733. WTRL/S and WR are also looking wack, 4/12/12 at the very highest and work WTRS and WR down from there. RRDS/L and FAW looking decent.

VDDP is more a seat-of-the-pants thing. Also, use Zentimings to view everything useful in the same place https://zentimings.protonrom.com/

And don't think too negatively about Geardown. It allows you to run way higher than you otherwise would at 1T, and is a big boost to stability. Intel guys don't even have it, 1T or bust (2T).

Yup, I had a feeling this was probably gonna be the answer. I just wanted to exhaust everything before moving on. As you said, its not a really big deal at all. But after investing so much time into OCing it, doesnt hurt to try every avenue

Im still cranking down main timings using that github guide. It said to adjust the tRRDS tRRDL tFAW tWR settings first, then tCL, then tRCD and tRP, then calculate your tRAS and tRC. Otherwise everything else is on auto.

 

[tabascosauz]

I honestly have no idea why he seems to think it "faster" to do some of the secondaries before the others. To make it easy on myself I just stick to the following groupings:

• CL
• tRCDs + tRP + tRAS + tRC - I can somewhat corroborate the tRAS' +2 rule for both ICs I own, so I stuck with that despite what some ppl think, it originally comes from Raja over at Asus
• RRDS/L + FAW
• WTRS/L + WR
• tRFC
• RDRDSCL + WRWRSCL
• VSOC, VDDP and VDDGs

Works well enough as a routine for most people. Add in RTP and CWL if you want. I don't usually test Geekbench and Linpack so for AIDA and membench they don't make a difference.

For the good ICs out there (that aren't Rev.E I guess, dont really know, Rev.E kinda loose on timings), his Tight recommendations for RRDS/L + FAW and WTRS/L + WR should be your minimum (highest) starting point. My Hynix stays there, but my Samsung E-die can do 4/4/16 and 4/10/12 I think. Need to check.

As with anything else, the memtesthelper guide isn't gospel either. Some things in there relating to procODT and VDDP for example are kinda generalized at best and sus at worst. procODT isn't a "range", and SR sticks behave differently from DR sticks. The best procODT is the one that works stable.

Also, not sure I've ever seen OCCT used as a serious memory test. HCI / Karhu / TM5 are your friends here.

 

[terminalinfinity]

I honestly have no idea why he seems to think it "faster" to do some of the secondaries before the others. To make it easy on myself I just stick to the following groupings:

• CL
• tRCDs + tRP + tRAS + tRC - I can somewhat corroborate the tRAS' +2 rule for both ICs I own, so I stuck with that despite what some ppl think, it originally comes from Raja over at Asus
• RRDS/L + FAW
• WTRS/L + WR
• tRFC
• RDRDSCL + WRWRSCL
• VSOC, VDDP and VDDGs

Works well enough as a routine for most people. Add in RTP and CWL if you want. I don't usually test Geekbench and Linpack so for AIDA and membench they don't make a difference.

For the good ICs out there (that aren't Rev.E I guess, dont really know, Rev.E kinda loose on timings), his Tight recommendations for RRDS/L + FAW and WTRS/L + WR should be your minimum (highest) starting point. My Hynix stays there, but my Samsung E-die can do 4/4/16 and 4/10/12 I think. Need to check.

As with anything else, the memtesthelper guide isn't gospel either. Some things in there relating to procODT and VDDP for example are kinda generalized at best and sus at worst. procODT isn't a "range", and SR sticks behave differently from DR sticks. The best procODT is the one that works stable.

Also, not sure I've ever seen OCCT used as a serious memory test. HCI / Karhu / TM5 are your friends here.

Cool. I'll go back to work on the main timings and post up any questions I incur here. Thanks for the help

Speaking of procODT, I've been seeing how far I can reduce it from 60 which was where I was originally stable. Im down to 48 which has helped with temps I think. Is this a bad strategy?

OCCT was from, his guide as well LOL. Since I had it and Memtest (on DRAM calculator) already seemed like a good 1-2 test. I'll add one of the more used ones from here and the Ryzen OC spreadsheet

Zen RAM OC Leaderboards

docs.google.com

Update:
So I'm doing final verification of stability, but I think I've settled on 3733 14-13-8-13-29 as my lowest stable main timings.
I guess TRC is next. I'm thinking I should try tRP+tRAS first and keeping adding 1 until stable.

 

[terminalinfinity]

UPDATE #2: I think I've pretty much got everything dialed in. Is there any gains to be had in trying to lower the other subtimings some more?

Just waiting on full verification of stability. Passed 9 passes in TM5, 1 hour in OCCT, 1000% on all threads coverage in HCI Memtest, and now up to 1000% in Karhu (Bought it btw thanks for the suggestion @tabascosauz ). Will be going for 10000% in Karhu before declaring it 100% stable.