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Micron Tapes Out 128-layer 3D NAND Flash Memory

Micron Technology has taped out its 4th generation 3D NAND flash memory with 128 layers. This paves the way for mass production and product implementations in 2020. The 4th gen 3D NAND by Micron continues to use a CMOS-under-array design, but with Replacement Gate (RG) Technology instead of Floating Gate, which Micron and the erstwhile IMFlash Technology had been using for years. Micron is currently mass-producing 96-layer 3D NAND flash, and TLC remains the prominent data-storage physical layer despite the advent of QLC (4 bits per cell).

Micron comments that this 4th gen 128-layer 3D NAND will be a stopgap restricted to a select few applications, and may not see the kind of adoption as its current 96-layer chips. The company appears to be more focused on its evolution, possibly the 5th generation 3D NAND, which are expected to bring tangible cost-per-bit gains for the company, as it transitions to a newer silicon fabrication node, and implements even newer technologies besides RG. "We achieved our first yielding dies using replacement gate or "RG" for short. This milestone further reduces the risk for our RG transition. As a reminder, our first RG node will be 128 layers and will be used for a select set of products. We don't expect RG to deliver meaningful cost reductions until FY2021 when our second-generation RG node is broadly deployed. Consequently, we are expecting minimal cost reductions in NAND in FY2020. Our RG production deployment approach will optimize the ROI of our NAND capital investments," said Sanjay Mehrotra, CEO and president of Micron.

Yangtze Memory Begins Mass-production of 64-layer 3D NAND Flash Memory

Yangtze Memory Technologies (YMTC), a Chinese state-backed semiconductor company founded in 2016 as part of the Chinese Government's tech-independence push, has commenced mass-production of 64-layer 3D NAND flash memory chips, at a rate of 100,000 to 150,000 wafers per month leading into 2020. The 64-layer 3D NAND chips are based on YMTC's "in-house" Xtracking architecture. The company is already developing a 128-layer 3D NAND flash chip, and is skipping 96-layer along the way.

YMTC's capacity will be augmented by a new fab being built by its parent company, Tsinghua Unigroup. Tsinghua is a state-owned company which holds a controlling 51 percent stake in YMTC, and is a beneficiary of China's National Semiconductor Industry Investment Fund. When it goes online in 2021-22, the new Tsinghua fab, located in Chengdu, will augment YMTC's capacity by an additional 100,000 12-inch wafers per month. Its existing fab in Nanjing will also receive a capacity expansion.

SK Hynix Reports Second Quarter 2019 Results

SK hynix Inc. today announced financial results for its second quarter 2019 ended on June 30, 2019. The consolidated second quarter revenue was 6.45 trillion won while the operating profit amounted to 638 billion won and the net income 537 billion won. Operating margin for the quarter was 10% and net margin was 8%.

As demand recovery did not meet expectations and price declines were steeper than expected, the revenue and the operating profit in the second quarter fell by 5% and 53%, respectively, quarter-over-quarter (QoQ). DRAM bit shipments increased by 13% QoQ as the Company actively responded to the mobile and PC DRAM markets, where demand growth was relatively high. However, DRAM prices remained weak and the average selling price dropped by 24%. For NAND Flash, the bit shipments increased by 40% QoQ because of demand recovery due to price declines, while the average selling price decreased by 25%.

Toshiba and Western Digital Readying 128-layer 3D NAND Flash

Toshiba and its strategic ally Western Digital are readying a high-density 128-layer 3D NAND flash memory. In Toshiba's nomenclature, the chip will be named BiCS-5. Interestingly, despite the spatial density, the chip will implement TLC (3 bits per cell), and not the newer QLC (4 bits per cell). This is probably because NAND flash makers are still spooked about the low yields of QLC chips. Regardless, the chip has a data density of 512 Gb. With 33% more capacity than 96-layer chips, the new 128-layer chips could hit commercial production in 2020-21.

The BiCS-5 chip reportedly features a 4-plane design. Its die is divided into four sections, or planes, which can each be independently accessed; as opposed to BiCS-4 chips that use a 2-plane layout. This reportedly doubles the write performance per unit-channel to 132 MB/s from 66 MB/s. The die also reportedly uses CuA (circuitry under array), a design innovation in which logic circuitry is located in the bottom-most "layer," with data layers stacked above, resulting in 15 percent die-size savings. Aaron Rakers, a high-technology industry market analyst with Wells Fargo, estimates that Toshiba-WD's yields per 300 mm wafer could be as high as 85 percent.
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