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Upcoming Hardware Launches 2021 (Updated Jun 2021)
(222 Comments) »Introduction
In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.
Last Update (Jun 14th):
- Updated AMD Cezanne Ryzen 5000G
- Updated AMD Zen 3+
- Updated AMD Zen 4
- Updated AMD Zen 5
- Updated Intel Alder Lake
- Added Intel Raptor Lake
- Updated Intel Meteor Lake
- Updated Intel Sapphire Rapids
- Added AMD Radeon RX 6600 / RX 6600 XT
- Added AMD Radeon RX 6400 Series
- Updated AMD Radeon Instinct MI200
- Updated AMD RDNA3
- Updated Intel DG2
- Updated HBM3 Memory
- Updated TSMC 4 nanometer
- Added TSMC 1-nanometer
- Updated Samsung 5 nanometer
- Updated Micron 176-layer NAND
- Updated Toshiba/WD PLC NAND Flash
- Updated Samsung 176-layer NAND
- Removed launched products: RTX 3070 Ti and RTX 3080 Ti, RX 6700 XT, RX 6000 Mobile, Radeon Pro W6800, X570S chipset, Micron 128-layer NAND flash
Processors
AMD Ryzen 5000G APUs for Desktop (Cezanne) [updated]
- Release Date: August 5, 2021
- These are desktop variants of the already-launched Ryzen 5000H laptop CPUs
- Ryzen 7 5700G: 8c/16t, 3.8 GHz Base, 4.6 GHz Boost, 65 W, $359
- Ryzen 5 5600G: 6c/12t, 3.9 GHz Base, 4.4 GHz Boost, 65 W, $259
- Ryzen 3 5300G: 4c/8t, 3.6 GHz Base, 4.2 GHz Boost, 65 W, not available for DIY
- "GE" models are 35 W
- OEM only at this time, DIY in August
AMD Lucienne Zen 2 APUs / Ryzen 5000
- Release Date: probably 2021
- Successor to "Renoir"
- Built on Zen 2 CPU cores, but still branded "Ryzen 5000"
- The model number scheme goes as 5x00U, where if "x" is an odd number, the chip is "Zen 2 Lucienne" based, and if it's an even number, it is "Zen 3 Cezanne" based
- Uses Vega iGPU
- Built on slightly refined 7 nm process, but not N7P or N7+
- Ryzen 3 5300U: 4c/8t, 2.6 GHz base, 3.85 GHz boost, 4 MB L3, 10-25 W TDP, 6 CU @ 1.5 GHz
- Ryzen 5 5500U: 6c/12t, 2.1 GHz base, 4.0 GHz boost, 8 MB L3, 10-25 W TDP, 7 CU @ 1.8 GHz
- Ryzen 7 5700U: 8c/16t, 1.8 GHz base, 4.3 GHz boost, 8 MB L3, 10-25 W TDP, 8 CU @ 1.9 GHz
- For other Ryzen 5000 U models, check the Cezanne section
- Built on TSMC 7 nm process, N7
AMD Zen 3 Threadripper "Genesis Peak"
- Release Date: August 2021
- Codename: Genesis Peak / Chagall
- Built on Zen 3 CPU cores
- Lineup starts with 16 cores, possibly up to 64
- Should be compatible with existing TRX40 motherboards (after BIOS update)
AMD Zen 3+ / Rembrandt APUs / Ryzen 6000 Series [updated]
- Release Date: Unknown
- 6 nanometer production process
- 12 RDNA2 CUs, with 768 stream processors
- Uses "3D V-Cache", which is a cache die (64 MB) stacked on top of each CCX (compute die)
- +15% gaming performance increase
AMD Zen 4 / Ryzen 7000 Series [updated]
- Release Date: mid/late 2022
- Launched around same time as RDNA3 GPU architecture
- "In Design" as of Nov 2018
- "On Track" for 2021 launch as of Dec 9, 2019, possibly not true anymore
- 5 nm TSMC process, possibly EUV
- Desktop codename: "Raphael"
- DDR5 memory support
- Improves IPC by up to 29%
- Server platform codenamed "Genoa", 320 W TDP, up to 400 W
- Server socket: SP5, 6096-pin LGA
- Up to 64 cores for EPYC
- Desktop changes socket to AM5
- PCI-Express Gen 5
- More cores per chiplet
- Support for AVX512 instructions, also BFloat16 and "other ISA extensions."
- Uses 3rd generation Infinity Fabric, which adds cache-coherent unified memory
- Nov 2020 statement from AMD: "Zen 4 is going to have a similar long list of things, where you look at everything from the caches, to the branch prediction, [to] the number of gates in the execution pipeline. Everything is scrutinized to squeeze more performance out."
- Adds support for USB 4.0
AMD Zen 5 / Ryzen 8000 Series [updated]
- Release Date: 2022
- 5 nm or 3 nm TSMC process
- DDR5 memory support
- PCI-Express Gen 5
- APU codename: "Rembrandt"
- Codename "Strix Point" could feature big.LITTLE core design, similar to Alder Lake
- Another codename: "Granite Ridge"
- Uses Socket SP5 for server, desktop uses Socket AM5
- Possibly all APUs (with integrated graphics)
Intel Willow Cove and Golden Cove Cores
- Release Date: 2021
- Succeeds "Sunny Cove"
- Willow Cove improves on-die caches, adds more security features, and takes advantage of 10 nm+ process improvements to increase clock speeds versus Sunny Cove
- Golden Cove will add significant single-thread (IPC) increases over Sunny Cove, add on-die matrix multiplication hardware, improved 5G network-stack HSP performance, and more security features than Willow Cove
Intel Alder Lake [updated]
- Release Date: October 2021
- Will launch alongside new Windows OS update
- Mixes CPU cores of various processing power and energy consumption, similar to the Big.Little-like designs for mobile devices
- Combines up to eight Golden Cove with up to eight Gracemont (Atom) cores
- These cores have two different instruction sets; for example, Golden Cove has AVX-512, TSX-NI, and FP16, which Gracemont lacks
- 10 nm+ SuperFin process
- Uses Socket LGA1700
- Existing Intel coolers not compatible due to different layout
- Alder Lake for desktop: 37.5 mm x 45 mm package
- Desktop CPUs come in 125 W and 80 W
- Up to 20% single-threaded performance uplift
- Could use Foveros 3D Stacking technology
- Mobile SKU Stack: 19 variants, ranging from 1C+4c+48 EU all the way up to 8C+8c+32EU, and 6C+8c+96EU
- TDPs range from 5 W to 55 W
- Prototype: 16c/32t, 1.8 GHz base, 4.0 GHz boost, 12.5 MB L2, 30 MB L3
- Another prototype: 8c/16t, 2.99 GHz on big cores
- Another prototype: 16c/24t, 8 big cores with HT, 8 small cores without HT. 4.6 GHz with 2 cores active, 4.4 GHz with 4c and 4.2 GHz with 6c, PL1=125 W, PL2=228 W
- Mobile TDP 55 W, 64 T and 115 W, depending on SKU
- Includes Gen12 Xe iGPU, running at 1.5 GHz
- DDR5 memory support, up to DDR5-4800, overclocks seen of DDR5-6400
- Also DDR4-3200, LPDDR4X, LPDDR5X
- Clocks up to 4.7 GHz
- PCI-Express 5.0 support (16x PCIe 5.0, 4x PCIe 4.0)
- DMI operates at PCIe Gen 4
- Memory controller uses Gear 1 / Gear 2 system introduced with Rocket Lake
- Includes CLDEMOTE instruction to invalidate cache lines
Intel Raptor Lake [added]
- Release Date: Q4 2022
- Successor to Alder Lake
- Uses "enhanced" Golden Cove cores, known as "RPC" / "Raptor Cove"
- Better IPC, frequency, perf/W than Alder Lake
- big.LITTLE design
- Probably 8 big + 16 little cores
- Little cores are Gracemont, same as Alder Lake
- DDR5-5600 and faster
- Competitor to AMD's Zen 4
- Uses same Socket LGA1700 as Alder Lake
Intel Sapphire Rapids [updated]
- Release Date: H2 2021
- Successor to Cooper Lake
- For enterprise / data center
- 10 nm+ SuperFin production process
- 56 cores, 112 threads using two dies
- EMIB to connect the dies using an active interposer
- Another leak suggests up to 80 cores across 4x 20-core chiplets
- Yet another leak talks about 60 cores with 4x 15-core chiplets
- Uses Socket LGA4677 or LGA4189
- Supports 1, 2, 4 and 8 Socket configurations
- 8-channel DDR5 memory, DDR5-4800
- HBM memory supported, 1 TB/s, 64 GB HBM2E per socket
- Golden Cove CPU cores
- 350 W max TDP
- ES clocked at 2 GHz
- PCIe 5.0, 80 lanes
- CXL 1.1 support, 4x x16 devices
- DLBoost, Enhanced SGX, improved Cryptographic Instructions
- Platform name: Eagle Stream
- Includes CLDEMOTE instruction to invalidate cache lines
Intel Grand Ridge
- Release Date: 2022 or later
- Produced on 7 nm HLL+ process
- Successor to Atom "Snow Ridge"
- 24 cores across 6 clusters with 4 cores each
- 4 MB L2 per cluster, plus L3 cache
- Uses Gracemont CPU core
- Dual-channel DDR5
- PCI-Expres Gen 4 with 16 lanes
Intel Elkhart Lake
- Release Date: unknown
- Produced on 10 nm process
- Designed for next-gen Pentium Silver and Celeron processors
- CPU cores use Tremont architecture
- GPU uses Gen 11
- Dual-core and quad-core configurations
- Single-channel memory controller with DDR4 and LPDDR4/x support
- Engineering sample: 1.9 GHz, 5/9/12 W TDP
Intel Meteor Lake [added]
- Release Date: 2023
- Taped in as of May 2021
- Compute tile will be taped out in Q2-2021
- Succeeds "Alder Lake"
- 7 nm Intel production process
- New microarchitecture, more advanced than "Willow Cove", possibly "Golden Cove"
- Hybrid processor—big.LITTLE architecture
- As of late 2020, Intel is adding support for Meteor Lake to the Linux Kernel
- Multi-chip-module using Foveros packaging technology
- Produced on various processes, possibly at different fabs, even non-Intel
Intel Jasper Lake
- Release Date: 2021
- Uses Tremont architecture
- 10 nm production process
- Successor to Gemini Lake
- ES: 4c/4t, 1.1 GHz Base, 1.12 GHz Boost
- Dual-channel DDR4 memory support
- Pentium Silver J6005: 4c/4t, 2 GHz base, 3 GHz boost, 4 MB L2
- Celeron J5105: 2 GHz vase, 2.8 GHz boost, 4 MB L2
- Celeron J4505: 2c/2t, 2 GHz base, 2.9 GHz boost 4 MB L2
- Pentium Silver N6000 Mobile: 4c/4t, 1.1 GHz base, 3.1 GHz boost, 4 MB L2
- Celeron N5100 Mobile: 1.1 GHz base, 2.8 GHz boost
- Celeron N4500 Mobile: 2c/2t, 1.1 GHz base, 2.8 GHz boost
- Gen 11 iGPU with 32 EU
- Used in Intel NUC11
Intel Lunar Lake
- Release Date: 2023 or 2024
- Succeeds "Meteor Lake"
Intel Granite Rapids
- Release Date: 2022
- Successor to Sapphire Rapids
- 8-channel DDR5
- For enterprise / data center
- PCIe 5.0
- Probably 7 nm+ process
- Platform name: Eagle Stream
VIA CenTaur / Zhaoxin KaiXian
- Release Date: H2 2020
- Eight-core 64-bit CPU, 2.5 GHz
- AVX-512 supported
- 16 nm FinFET TSMC
- 195 mm² die size
- Use LGA socket
- Codename: "CHA", pronounced "C-H-A"
- Separate AI co-processor "NCORE"
- All cores + NCORE connected using a ring bus
- Integrated VIA S3 graphics with DirectX 11.1
- 16 MB shared L3 cache
- Four-channel DDR4-3200 memory support
- 44 PCI-Express 3.0 lanes
- Sold as Zhaoxin KaiXian KX-6780A in China (end of Jan 2020): 8 core, 8 threads, 2.7 GHz, 8 MB cache, dual-channel DDR4-3200
- Southbridge integrated
- Multi-socket capable
Graphics / GPUs
NVIDIA RTX 3050 / RTX 3050 Ti
- Release Date: unknown, possibly 2021
- RTX 3050: 2048 cores, 713 to 1530 MHz base, 1057 to 1740 MHz Boost, 4 GB GDDR6
- RTX 3050 Ti: 2560 cores, 735 to 1463 MHz base, 1035 to 1695 MHz Boost, 6 GB GDDR6
- 35 - 80 W TDP
NVIDIA RTX 3060 Ultra
- Release Date: 2021
- Same GA104 GPU as RTX 3060 Ti and RTX 3070
- 12 GB GDDR6
- 192-bit or 256-bit memory bus
- $449
NVIDIA RTX 3070 Super / RTX 3080 Super
- Release Date: 2021
- No details known
NVIDIA Ampere with more VRAM
- Release Date: 2021
- Possibly canceled as of Oct 2020
- RTX 3080 with 20 GB memory (instead of 10 GB)
- RTX 3070 with 16 GB memory (instead of 8 GB)
NVIDIA Ampere Refresh
- Release Date: unknown
- NVIDIA is moving their existing designs from Samsung 8 nm to TSMC 7 nm
NVIDIA Hopper
- Release Date: unknown
- Successor to "Ampere" architecture, or next compute-only architecture
- MCM (multi-chip module) GPU packages
- Seems to be for workstation/compute only
NVIDIA Ada Lovelace
- Release Date: unknown
- Successor to "Ampere" architecture, possibly gaming-only focused
- AD102: 18,432 shaders, 144 SMs
- 5 nanometer process
AMD Radeon RX 6600 / RX 6600 XT [added]
- Release date: 2021
- Based on 7 nanometer Navi 23 GPU
- 11 billion transistors, 237 mm² die size
- 32 CUs, 2048 cores, 128 TMUs, 32 ROPs
- RX 6600 non-XT: 1792 cores, 112 TMUs, 32 ROPs
- 8 GB 128-bit GDDR6 + 32 MB on-die L3 cache
- Interface PCIe 4.0 x8 or x16
AMD Radeon RX 6500
- Release date: unknown
- 40 compute units / 2560 stream processors
- 192-bit GDDR6 memory
- 7 nanometer production process
- RDNA2 architecture
- Codename "Navy Flounder"
- Below $250
AMD Radeon RX 6400
- Release date: unknown
- Codename "Beige Goby"
AMD Mining GPUs
- Release date: unknown, probably sooner than later
- Based on Navi 10 and Navi 12
- 40 CU, 2560 stream processors
- Most likely Navi 12 without HBM2
AMD Radeon Instinct MI200 [updated]
- Release date: 2021
- Codename: Aldebaran
- Uses CDNA2 compute architecture
- Uses a MCM design—multiple dies in one package, at least two dies confirmed
AMD Navi 31
- Release date: unknown, probably 2022 or late 2021
- Dual-chiplet design
- Uses RDNA3 architecture
- Each chiplet has 80 CU / 5120 cores
- Total 10240 cores
- Possibly RT improvements
AMD RDNA 3 [updated]
- Release Date: 2022
- Tapeout: End of 2021
- "Advanced Node", probably TSMC 6 nm or 5 nm, possibly EUV
- Launches at around the same time as Zen 4
- Big focus is power efficiency
- RX 7900 XT: 40% faster than RX 6900 XT, in some cases up to 60-80%
- Chiplet design with discrete IO and compute dies similar to Ryzen
- Target is +50% perf/W
Intel DG2 discrete GPU [updated]
- Release Date: 2021, probably Q3 or Q4
- Successor to DG1 Intel Xe discrete GPU
- Comes to Alder Lake-P laptops first
- Package: BGA2660
- Die size: 190 mm²
- DG12 is 384 EU, 190 mm², 6/12 GB GDDR6, 192-bit
- EU counts: 512, 384, 256, 196 and 128
- 2.2 GHz base clock, 16 GB GDDR6, 256-bit, 275 W TDP with 8+6 pin-power
- Mobile: up to 1.8 GHz Turbo, 100 W TDP
- 8 / 16 GB GDDR6 memory, 192-bit
- On Alder Lake-P it uses a PCIe Gen 4 x12 link between Tiger Lake H and DG2
- Probably produced at TSMC, possibly 7 nm
- Intel's DLSS competitor to be called "XeSS"
- Lower 128 and 256 EU cards will follow in 2022
Intel Ponte Vecchio
- Release Date: 2021 or 2022
- Discrete GPU
- Produced on 7 nanometer production process
- Probably not 7 nanometer Intel, but 7 nm TSMC or even 6 nm TSMC
- Multiple GPU dies will be combined into a single accelerator
- Architected "for HPC modeling and simulation workloads and AI training"
- Workloads can be processed by GPU and CPU at the same time, using Intel oneAPI
- Foveros packaging technology
- Supports DirectX 12 mesh shaders
- "petaflops in your palm"
- Will be installed in Leibniz Supercomputing Centre in 2022
- Xe link to combine multiple GPUs (CXL interconnect)
- Up to 47 silicon tiles combined to form one big chip
- Xe HPC photo suggests that there's two types of memory on the interposer, one of them being HBM
Intel Jupiter Sound
- Release Date: 2022
- Discrete GPU
- Produced on 10 nanometer production process
- Successor to Arctic Sound
Zhaoxin Discrete GPU
- Release Date: unknown
- Discrete GPU
- Produced on 28 nanometer production process
- 70 W TDP
- Based on VIA S3 graphics IP
Chipsets
Memory
DDR5 System Memory
- Release Date: Probably Q3 2021
- JEDEC standard finalized as of Jul 15th 2020
- Demo'd in May 2018 by Micron: DDR5-4400
- Samsung 16 Gb DDR5 DRAM developed since February 2018
- Samsung has completed functional testing and validation of an LPDDR5 prototype: 10 nm class, 8 Gbit; final clocks: DDR5-5500 and DDR5-6400
- Samsung has started 16 Gb LPDDR5 mass production in Aug 2020
- SK Hynix 4800–5600 Mbps, 1.1 V
- SK Hynix also has 16 Gb DDR5-5200 samples ready, 1.1 V, mass production expected 2020
- As of March 2021, Hynix has started mass production of LPDDR5 18 GB (yes, 18, not 16), up to DDR5-6400
- April 2020: Hynix has 8.4 Gbps DDR5, minimum density per die is 8 Gbit, maximum is 64 Gbit
- ECC is now supported by all dies (no longer specific to server memory modules)
- SK Hynix demonstrated DDR5 RDIMM modules at CES 2020: 4800 MHz, 64 GB
- Micron is shipping LPDDR5 for use in Xiaomi phones (Feb 2 2020); 5.5 Gbps and 6.4 Gbps
- Samsung has begun production for LPDDR5 for mobile devices (Feb 25 2020); 16 GB, 5.5 Gbps
- Galax,Team Group, Jiahe Jinwei, Longsys, Asgard: working on DDR5 memory, using Micron chips
- Kingston working on DDR5 overclocking
- ADATA: up to 8400 MT/s and up to 64 GB
- 4800–6400 Mbps
- Expected to be produced using 7 nm technologies
- 32 banks, 8 bank groups
- 64-bit link at 1.1 V
- Burst length doubled to BL16
- Bank count increased from 16 to 32
- Fine grain refresh feature
- Improved power efficiency enabled by Vdd, going from 1.2 V to 1.1 V as compared to DDR4
- On-die ECC
- Voltage regulators on the DIMM modules
- AMD DDR5 memory support by 2021/2022, with Zen 4
HBM2E Graphics Memory
- Release Date: 2020
- Used on products: 2021
- Offers 3.2 Gbps per pin (33% faster than HBM2)
- Rambus offers a 4.0 Gbps memory interface controller
- Samsung Flashbolt: 16 Gb per die, 8-layers stacked, 16 GB per chip with 410 GB/s bandwidth
- Hynix: 460 GB/s, 3.6 Gbps, eight 16 Gb chips are stacked for a single 16 GB chip
- Hynix: mass production has started as of July 2020
HBM3 Graphics Memory [updated]
- Release Date: originally "not before 2019", no updated timing is known
- Double the memory bandwidth per stack (4000 Gbps expected)
- Expected to be produced using 7 nm technologies
- Hynix: 5.2 Gbps per pin, stack bandwidth 665 GB/s
HBMNext Memory
- Release Date: late 2022 or 2023
- JEDEC work in progress
- Micron involved
Silicon Fabrication Tech
TSMC 7 nanometer+
- Release Date: Q4 2019
- TSMC N7+ successor to original 7 nm node
- Uses EUV (Extreme Ultra Violet)
- 15%–20% more density and improved power consumption over N7
TSMC 6 nanometer
- Release Date: unknown
- Backwards compatible with 7 nm process—no new design tools needed
- Uses EUV (Extreme Ultra Violet), up to four EUV layers
- 18% higher logic density than N7
TSMC 5 nanometer
- Release Date: March 2020 to tape-out customer designs
- Risk production as of Q2 2019
- High volume production: Q2 2020
- Uses TSMC's second implementation of EUV (Extreme Ultra Violet)
- Up to 1.8x the density of 7 nm
- Up to 14 layers
- +15% higher clocks
- 30% better bower than N7
- Intel might be a customer of this node
- N5P "Plus" node: improvement to N5 while staying on 5 nm, 84%–87% increase in transistor densities over N7
TSMC 5 nanometer+
- Release Date: 2021
- High-volume production in Q4 2020
- Uses EUV (Extreme Ultra Violet)
TSMC 4 nanometer [updated]
- Volume production: Q3 2021
- Mass production: 2022 or 2023
- Codename "N4"
- Uses EUV lithography
TSMC 3 nanometer
- April 2020: on track
- Risk production: H2 2021
- Volume production: H2 2022
- FinFET technology
- Uses TSMC's third implementation of EUV (Extreme Ultra Violet)
- 10%–15% speed improvement at iso-power or 25%–30% power reduction at iso-speed, compared to N5
- 30,000 wafers per month at the start, 105,000 by 2023
- 12-inch wafer size
TSMC 3 nanometer+
- Release date: 2023
- First client will be Apple
TSMC 2 nanometer
- Release Date: 2023 (risk production)
- June 2020: TSMC is accelerating R&D
- Sep 2020: fab construction has begun
- Will use Gate-All-Around (GAA) technology
- Multi-bridge channel field effect transistor (MBCFET) architecture
TSMC 1 nanometer [added]
- Release Date: Unknown
- Uses Semi-metal bismuth for contact electrodes
Samsung 6 nanometer
- Release Date: unknown
- First product taped out as of Q2 2019
- Uses EUV (Extreme Ultra Violet)
- Special variant for customers
Samsung 5 nanometer [updated]
- Release Date: 2020
- Ready for customer sample production as of Q2 2019
- In production as of Q4 2020
- Yields are challenging as of Q2 2020
- Plans to build fab in Austin TX, for $18B
- Uses EUV (Extreme Ultra Violet)
- Up to 25% the density of 7 nm
- 20% lower power consumption
- 10% higher performance
Samsung 3 nanometer
- Release Date: 2022
- 50% less power while delivering 30% more performance
- 45% less silicon space taken per transistor (vs. 7 nm)
Intel 7 nanometer
- Release Date: 2023
- Succeeded by 7 nm+ node in 2022, and 7 nm++ in 2023
- Uses EUV (Extreme Ultra Violet)
- 4x reduction in design rules
- Planned to be used on multiple products: CPU, GPU, AI, FPGA, 5G networking
- Jan 2021: Intel reports "issues fixed"
Other
Hynix 4D NAND
- Release Date: H1 2019
- Developed by SK Hynix
- Sampling in Q4 2018
- Products demonstrated at CES 2020: Platinum P31 M.2 NVMe and Gold P31—PCIe 3.0 x4, using flash, DRAM, and controller made by Hynix, over 3 GB/s read/write.
- Reduces chip physical size while increasing capacity
- Supports TLC and QLC
- 30% higher write and 25% higher read performance
- 1.2 V
- 1st generation: 96 stacks, 1.2 Gbps per pin, 512 Gbit TLC
- 128 stacks in development, scales up to 512 stacks
Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC) [updated]
- Release Date: Delayed to 2025
- Stores an additional bit of information per cell (compared to QLC)
- 32 states per cell
- Will enable even cheaper SSDs, probably at a performance cost
Toshiba XL-Flash
- Developed by Toshiba
- Uses existing SLC flash technology to improve latencies
- 1/10th the read latency of TLC
- Good for random IOPS and better QoS at shallow queue depth
- Can combine SLC and TLC/QLC for tiered, cost-optimized storage
- Intel Optane memory competitor
- 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
- 4 KB page size for more efficient operating system reads and writes
- 16-plane architecture for more efficient parallelism
- Fast page read and program times
Micron 176-layer 3D NAND Flash [updated]
- Release Date: Nov 2020 (volume shipments)
- Products: Jun 2021
- CMOS-under-array design
- 30% smaller die size
- 35% improved read/write latency
- 1600 MT/s transfer rate
Hynix 176-layer 3D NAND Flash
- Release Date: 2020
- 512 Gbit TLC
- 20% faster read speed per cell
- 1600 MT/s transfer rate
Toshiba 128-layer 3D NAND Flash
- Release Date: 2020 or 2021
- Developed by Toshiba and partner Western Digital
- Called BiCS 5
- According to a press release in Feb 2020, this is actually a 112 layer stacking process
- Cells are TLC (not QLC)
- Chip density: 512 Gb
- Write performance per channel doubled to 133 MB/s
Toshiba 162-layer 3D NAND Flash
- Release Date: 2021
- Developed by Toshiba and partner Western Digital
- Called "6th generation"
- 10% better lateral cell array density
- 40% reduction in die size compared to 112-layer technology
- 10% improvement to read latency
- Uses Circuit Under Array CMOS placement and 4-plane operation
- Reduces cost per bit by 70%
Intel 144-layer 3D NAND Flash
- Release Date: 2020
- Supports QLC, but can be configured to work as TLC or SLC
- SSD codename "Keystone Harbor"
- PLC (5-bit per cell) technology development is underway
- Optane product codename "Alder Stream", PCIe Gen4
SK Hynix 128-layer 3D NAND Flash
- Mass Production: July 2020
- Up to 1 Tb TLC flash per chip
- Data rate up to 1400 Mbps at 1.2 V
- Products will be 2 TB client SSD with in-house controller and 16 TB / 32 TB NVMe datacenter SSDs.
Samsung 176-layer 3D NAND Flash [updated]
- Release Date: 2021
- 7th generation V-NAND
- Originally known as "160"-layer 3D NAND, now 176-layer
- Will be used on PCIe 4.0 and 5.0 SSDs
Intel CXL Interconnect
- New interconnect for high-bandwidth devices like GPUs
- Targeted at enterprise and servers
- Competitor to NVLink, Infinity Fabric, and PCI-Express
- Uses PCIe physical layer
- Link layer designed for low latency
- 32 Gbps per lane, per direction (like PCIe Gen 5.0)
PCI-Express 5.0
- Specification released end of May 2019
- Products not expected before 2020/2021
- 32 GT/s bandwidth per lane, per direction (4x the bandwidth of PCIe 3.0)
- 128/130 bit encoding (= 1.5% overhead)
- Implements electrical changes to improve signal integrity and mechanical performance of connectors
- Physical connector is backward compatible
- Signalling is backward compatible with all previous PCIe versions
PCI-Express 6.0
- Specification targeted for 2021
- Spec version 0.5 published as of Feb 2020
- Spec version 0.7 published as of Nov 2020
- 64 GT/s raw bit rate, up to 256 GB/s with x16
- Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Maintains backwards compatibility with all previous generations of PCIe technology
- New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
USB 4.0
- Release Date: end of 2020
- Specification Released: September 2019
- Conceptually similar to Thunderbolt 3
- Up to 40 Gbps speeds using two-lane operation
- Multiple data and display protocols can share bandwidth
- Uses USB Type-C connector
- Backwards compatible with USB 2.0, 3.0, 3.1, 3.2, and Thunderbolt 3
- Resulting connection scales to the best mutual capability of the devices being connected