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Upcoming Hardware Launches 2021 (Updated Nov 2021)
(243 Comments) »Introduction
In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.
Last Update (Nov 22nd):
- Updated AMD Zen 4
- Added AMD EPYC Milan-X
- Updated Intel Raptor Lake
- Updated Intel Sapphire Rapids
- Updated Intel Meteor Lake
- Updated Intel H670, B660 & H610 Chipsets
- Updated Intel DG2 Discrete Graphics
- Added DDR6 System Memory
- Added GDDR6+ and GDDR7 Graphics Memory
- Added TSMC 4 nm+
- Updated TSMC 3 nanometer
- Removed launched products: Alder Lake, Golden Cove, AMD MI200, Intel Z690, DDR5, HBM2E, PCI-Express 5.0, Micron 176-layer NAND, Intel 144-layer NAND, Hynix 128-layer NAND
Processors
AMD Lucienne Zen 2 APUs / Ryzen 5000
- Release Date: probably 2021
- Successor to "Renoir"
- Built on Zen 2 CPU cores, but still branded "Ryzen 5000"
- The model number scheme goes as 5x00U, where if "x" is an odd number, the chip is "Zen 2 Lucienne" based, and if it's an even number, it is "Zen 3 Cezanne" based
- Uses Vega iGPU
- Built on slightly refined 7 nm process, but not N7P or N7+
- Ryzen 3 5300U: 4c/8t, 2.6 GHz base, 3.85 GHz boost, 4 MB L3, 10-25 W TDP, 6 CU @ 1.5 GHz
- Ryzen 5 5500U: 6c/12t, 2.1 GHz base, 4.0 GHz boost, 8 MB L3, 10-25 W TDP, 7 CU @ 1.8 GHz
- Ryzen 7 5700U: 8c/16t, 1.8 GHz base, 4.3 GHz boost, 8 MB L3, 10-25 W TDP, 8 CU @ 1.9 GHz
- For other Ryzen 5000 U models, check the Cezanne section
- Built on TSMC 7 nm process, N7
AMD Zen 3 Threadripper "Genesis Peak"
- Release Date: Delayed to 2022, maybe to wait for the new 3DV Cache cores
- Codename: Genesis Peak / Chagall
- Built on Zen 3 CPU cores
- Lineup: 24 cores, 32 cores and 64 cores
- Ryzen Threadripper PRO 5995WX: 64c/128t
- Ryzen Threadripper PRO 5945WX: 12c/24t
- Workstation version is available with 12 and 16 cores, too
- TDP of 280 W
- Should be compatible with existing TRX40 motherboards (after BIOS update)
- Workstation version uses WRX80 socket
- 8-channel DDR4 memory
- 128 PCIe 4.0 lanes on workstation, 64 on HEDT
AMD Zen 3+ / Rembrandt APUs / Ryzen 6000 Series
- Release Date: Q1 2022
- 6 nanometer production process
- 12 RDNA2 CUs, with 768 stream processors
- Uses "3D V-Cache", which is a cache die (64 MB) stacked on top of each CCX (compute die)
- 3D V-Cache expands L3 cache size (it's not a L4), the OS sees 96 MB cache
- 3D V-Cache die size is 6x6 mm.
- Improves performance by 4 to 25% in games
- Socket could be AM4 (likely) or AM5
EPYC Milan-X [added]
- Release Date: Q1 2022
- Produced on same 7 nm process as existing Zen 3 / Milan CPUs
- Adds "3D Infinity Cache", to triple L3 cache size
- Up to 64 Zen 3 cores
- Compatible with Socket SP3
AMD Zen 4 / Ryzen 7000 Series [updated]
- Release Date: mid/late 2022
- Launched around same time as RDNA3 GPU architecture
- "In Design" as of Nov 2018
- "On Track" for 2021 launch as of Dec 9, 2019, possibly not true anymore
- 5 nm TSMC process, possibly EUV
- Desktop codename: "Raphael"
- DDR5 memory support
- Improves IPC by up to 29%
- Server platform codenamed "Genoa", up to 96 cores, 320 W TDP, up to 400 W
- Server socket: SP5, 6096-pin LGA
- Up to 64 cores for EPYC
- Up to 16 cores for notebook (Raphael-H)
- Desktop platform goes up to 170 W, with 16 cores
- Desktop changes socket to AM5
- Socket AM4 coolers will be compatible with AM5
- Support for PCI-Express 5.0
- Genoa (EPYC Server) will also have CXL
- Bergamo uses Zen 4c on 5 nm with up to 128 cores
- More cores per chiplet
- All Zen 4 CPUs will have RDNA2 integrated graphics
- Support for AVX512 instructions, also BFloat16 and "other ISA extensions."
- "Enhanced Security Features"
- Improved thermal sensors and power management
- Uses 3rd generation Infinity Fabric, which adds cache-coherent unified memory
- Nov 2020 statement from AMD: "Zen 4 is going to have a similar long list of things, where you look at everything from the caches, to the branch prediction, [to] the number of gates in the execution pipeline. Everything is scrutinized to squeeze more performance out."
- Adds support for USB 4.0 (via separate chip)
AMD Zen 5 / Ryzen 8000 Series
- Release Date: 2022
- 5 nm or 3 nm TSMC process
- DDR5 memory support
- PCI-Express Gen 5
- APU codename: "Rembrandt"
- Codename "Strix Point" could feature big.LITTLE core design, similar to Alder Lake
- Another codename: "Granite Ridge"
- Uses Socket SP5 for server, desktop uses Socket AM5
- Possibly all APUs (with integrated graphics)
Intel Raptor Lake [updated]
- Release Date: Q4 2022
- Successor to Alder Lake
- Uses "enhanced" Golden Cove cores, known as "RPC" / "Raptor Cove"
- Better IPC, frequency, perf/W than Alder Lake
- L2 cache increased
- Up to 5.5 GHz
- big.LITTLE design
- Core i9-13900K: 24C (8+16) 32T, 36M L3, 32 EU, 125 W
- Core i9-13900: 24C (8+16) 32T, 36M L3, 32 EU, 65 W
- Core i7-13700K: 16C (8+8) 24T, 30M L3, 32 EU, 125 W
- Core i7-13700: 16C (8+8) 24T, 30M L3, 32 EU, 65 W
- Core i5-13500K: 14C (6+8) 20T, 24M, 32 EU, 125 W
- Core i5-13500: 14C (6+8) 20T, 24M, 32 EU, 65 W
- Core i5-13400: 10C (6+4) 16T, 21M, 24 EU, 65 W
- Core i3-13300: 4C (4+0) 8T, 12M, 32 EU, 65 W
- Pentium: 2C (2+0) 4T, 6M, 16 EU, 65 W
- Little cores are Gracemont, same as Alder Lake
- DDR5-5600 and faster
- Might also support DDR4
- Competitor to AMD's Zen 4
- Uses same Socket LGA1700 as Alder Lake
Intel Sapphire Rapids [updated]
- Release Date: 2022
- Ramp up: Q2 2022
- Successor to Cooper Lake
- For enterprise / data center
- 10 nm+ SuperFin production process, now called "Intel 7"
- Uses chiplet architecture
- All chiplets are connected through a mesh fabric to minimize latencies
- EMIB to connect the dies using an active interposer
- ES: 56 cores, 112 threads using two dies
- Another leak suggests up to 80 cores across 4x 20-core chiplets
- Yet another leak talks about 60 cores with 4x 15-core chiplets
- Engineering Sample: 20 Cores, 40 MB L2 cache, 75 MB L3 cache, 1.5 GHz
- 2 MB L2 cache per core
- Uses Socket LGA4677 or LGA4189
- Supports 1, 2, 4 and 8 Socket configurations
- 8-channel DDR5 memory, DDR5-4800
- HBM memory supported, 1 TB/s, 64 GB HBM2E per socket
- HBM can operate as DRAM cache or as additional DRAM memory, or HBM-only, without system DRAM
- Golden Cove CPU cores (same as Alder Lake)
- 350 W max TDP
- ES clocked at 2 GHz
- PCIe 5.0, 80 lanes
- CXL 1.1 support, 4x x16 devices
- DLBoost, Enhanced SGX, improved Cryptographic Instructions, FP16
- UPI bus improved: "UPI 2.0 is wider and faster", up to 4x 24 UPI links @ 16 GT/s
- Platform name: Eagle Stream
- Specific Sapphire Rapids variants will come with on-package HBM, also called "PMEM" (package memory)
- Includes CLDEMOTE instruction to invalidate cache lines
- Might support firmware updates without reboot
Intel Sapphire Rapids HEDT
- Release Date: Q3 2022
- High-end Desktop (HEDT) version of Sapphire Rapids Xeon
- Same underlying tech as Sapphire Rapids: 10 nm SuperFin, PCIe 5.0, DDR5
- Designed to combat AMD Threadripper
- Uses Intel W790 chipset
Intel Grand Ridge
- Release Date: 2022 or later
- Produced on 7 nm HLL+ process
- Successor to Atom "Snow Ridge"
- 24 cores across 6 clusters with 4 cores each
- 4 MB L2 per cluster, plus L3 cache
- Uses Gracemont CPU core
- Dual-channel DDR5
- PCI-Express Gen 4 with 16 lanes
Intel Elkhart Lake
- Release Date: unknown
- Produced on 10 nm process
- Designed for next-gen Pentium Silver and Celeron processors
- CPU cores use Tremont architecture
- GPU uses Gen 11
- Dual-core and quad-core configurations
- Single-channel memory controller with DDR4 and LPDDR4/x support
- Engineering sample: 1.9 GHz, 5/9/12 W TDP
Intel Meteor Lake [updated]
- Release Date: 2023 or 2024
- Taped in as of May 2021
- First test production: Nov 2021
- Succeeds "Alder Lake"
- New microarchitecture "Redwood Cove", two generations ahead of "Golden Cove"
- Hybrid processor—big.LITTLE architecture
- Multi-chip-module using Foveros packaging technology
- Produced on various processes, at different fabs, even non-Intel
- Four distinct tiles
- Compute tile on Intel 4 (7 nm)
- Graphics tile on TSMC N3, Intel Gen 12.7 architecture, 192 EUs
- SOC tile on TSMC
- Fourth tile might be something AI-related
- PCI-Express 5.0
- DDR5 + LPDDR5X
- As of late 2020, Intel is adding support for Meteor Lake to the Linux Kernel
Intel Jasper Lake
- Release Date: 2021
- Uses Tremont architecture
- 10 nm production process
- Successor to Gemini Lake
- ES: 4c/4t, 1.1 GHz Base, 1.12 GHz Boost
- Dual-channel DDR4 memory support
- Pentium Silver J6005: 4c/4t, 2 GHz base, 3 GHz boost, 4 MB L2
- Celeron J5105: 2 GHz vase, 2.8 GHz boost, 4 MB L2
- Celeron J4505: 2c/2t, 2 GHz base, 2.9 GHz boost 4 MB L2
- Pentium Silver N6000 Mobile: 4c/4t, 1.1 GHz base, 3.1 GHz boost, 4 MB L2
- Celeron N5100 Mobile: 1.1 GHz base, 2.8 GHz boost
- Celeron N4500 Mobile: 2c/2t, 1.1 GHz base, 2.8 GHz boost
- Gen 11 iGPU with 32 EU
- Used in Intel NUC11
Intel Lunar Lake
- Release Date: 2023 or 2024
- Succeeds "Meteor Lake"
Intel Granite Rapids
- Release Date: 2022
- Successor to Sapphire Rapids
- 8-channel DDR5
- For enterprise / data center
- PCIe 5.0
- Probably 7 nm+ process
- Platform name: Eagle Stream
VIA CenTaur / Zhaoxin KaiXian
- Release Date: H2 2020
- Eight-core 64-bit CPU, 2.5 GHz
- AVX-512 supported
- 16 nm FinFET TSMC
- 195 mm² die size
- Use LGA socket
- Codename: "CHA", pronounced "C-H-A"
- Separate AI co-processor "NCORE"
- All cores + NCORE connected using a ring bus
- Integrated VIA S3 graphics with DirectX 11.1
- 16 MB shared L3 cache
- Four-channel DDR4-3200 memory support
- 44 PCI-Express 3.0 lanes
- Sold as Zhaoxin KaiXian KX-6780A in China (end of Jan 2020): 8 core, 8 threads, 2.7 GHz, 8 MB cache, dual-channel DDR4-3200
- Southbridge integrated
- Multi-socket capable
Graphics / GPUs
NVIDIA RTX 3050 / RTX 3050 Ti
- Release Date: unknown, possibly 2021
- RTX 3050: 2048 cores, 713 to 1530 MHz base, 1057 to 1740 MHz Boost, 4 GB GDDR6
- RTX 3050 Ti: 2560 cores, 735 to 1463 MHz base, 1035 to 1695 MHz Boost, 6 GB GDDR6
- 35 - 80 W TDP
NVIDIA RTX 3060 Ultra
- Release Date: 2021
- Same GA104 GPU as RTX 3060 Ti and RTX 3070
- 12 GB GDDR6
- 192-bit or 256-bit memory bus
- $449
NVIDIA RTX 3060 Super, RTX 3070 Super / RTX 3080 Super / RTX 3090 Super
- Release Date: 2022, possibly CES in January
- RTX 3060 Super: 5632 cores, 12 GB GDDR6
- RTX 3070 Super: 5888 cores, 8 GB GDDR6X
- RTX 3080 Super: 8960 cores, 12 GB GDDR6X
- RTX 3090 Super: 10752 cores, 24 GB GDDR6X 21 Gbps, 400 W+
NVIDIA Ampere Refresh
- Release Date: unknown
- NVIDIA is moving their existing designs from Samsung 8 nm to TSMC 7 nm
NVIDIA Hopper
- Release Date: unknown
- Successor to "Ampere" architecture, or next compute-only architecture
- MCM (multi-chip module) GPU packages
- Uses TSMC 5 nanometer process
- Two dies, each with 288 SM for a total of 73,728 cores
- Seems to be for workstation/compute only
NVIDIA Ada Lovelace
- Release Date: not before 2022
- Successor to "Ampere" architecture, possibly gaming-only focused
- AD102: 18,432 shaders, 144 SMs
- 5 nanometer process at TSMC
- Up to 70 FLOP/s, more than 2 GHz
AMD Radeon RX 6500
- Release date: unknown
- 40 compute units / 2560 stream processors
- 192-bit GDDR6 memory
- 7 nanometer production process
- RDNA2 architecture
- Codename "Navy Flounder"
- Below $250
AMD Radeon RX 6400
- Release date: unknown
- Codename "Beige Goby"
AMD Mining GPUs
- Release date: unknown, probably sooner than later
- AMD BC-160, based on Navi 12 with 8 GB HBM2 at 4 Gbps, 2048-bit, 2304 cores, 36 CU
- "BC-160": BC=Blockchain Compute, 1=First Generation, 60=ETH Performance Range
- ETH Performance: 69.5 Mh/s @ 150 W TGP
- Overclocking supported through driver API
- 2x 8-pin power connector
- Another mining GPU expected based on Navi 10
- Most likely Navi 12 without HBM2
AMD Navi 31
- Release date: unknown, probably 2022 or late 2021
- Dual-chiplet design
- Uses RDNA3 architecture
- Each chiplet has 80 CU / 5120 cores
- Total 10240 cores
- Possibly RT improvements
AMD Radeon RX 7600 XT
- Release date: unknown
- Uses Navi 23 GPU (RDNA2)
- Optical shrink to 6 nm for better heat/efficiency
- Rest of specs identical to RX 6600 XT: 32 CU, 2048 cores, 128-bit GDDR6
AMD Radeon RX 7700 XT
- Release date: unknown
- Uses Navi 22 GPU (RDNA2)
- Optical shrink to 6 nm for better heat/efficiency
- Rest of specs identical to RX 6700 XT: 40 CU, 2560 cores, 192-bit GDDR6
AMD RDNA 3
- Release Date: 2022
- Tapeout: End of 2021
- "Advanced Node", probably TSMC 6 nm or 5 nm, possibly EUV
- Launches at around the same time as Zen 4
- Big focus is power efficiency
- RX 7900 XT: 40% faster than RX 6900 XT, in some cases up to 60-80%
- RX 7900 XT: 15,360 GPU cores (4x that of RX 6800)
- Chiplet design with discrete IO and compute dies similar to Ryzen
- Target is +50% perf/W
- Support for DisplayPort 2.0 (higher bitrate, 10K @ 60 or 2x 4K 144)
Intel DG2 discrete GPU [updated]
- Release Date: 2022, probably Q1 or Q2
- Successor to DG1 Intel Xe discrete GPU
- Will be released under the "Arc" brand name
- GPU codename "Alchemist"
- Comes to Alder Lake-P laptops first
- Package: BGA2660
- Die size: 190 mm²
- DG12 is 384 EU, 190 mm², 6/12 GB GDDR6, 192-bit
- EU counts: 512, 384, 256, 196 and 128
- 2.2 GHz base clock, 16 GB GDDR6, 256-bit, 275 W TDP with 8+6 pin-power
- Mobile: up to 1.8 GHz Turbo, 100 W TDP
- 8 / 16 GB GDDR6 memory, 192-bit
- DG2 with 256 EU offers GTX 1050 performance
- Another leak suggests the 512 EU version will compete with RTX 3070 Ti & RX 6700
- On Alder Lake-P it uses a PCIe Gen 4 x12 link between Tiger Lake H and DG2
- Produced on TSMC 6 nanometer process
- Intel's DLSS competitor to be called "XeSS"
- No mining lock
- Supports ray tracing, with hardware units
- Lower 128 and 256 EU cards will follow in 2022
- First price estimates: $825 and $650 for sligher weaker model
- Built on 6 nanometer process at TSMC
- At Intel Architecture Day 2021, Intel mentioned that they'll stop using "EU" as unit count. Instead the words used are "Vector Engines"
- "Matrix Engines" are hardware acceleration units for matrix math, similar to NVIDIA's Tensor Cores
- One Xe core is 128 shader cores, four such cores per slice, multiple slices per GPU
- A block diagram was shown with eight slices, which would bring the shader count to 4096, similar to RX 6800 Series or RTX 2080 Ti
- Overclocking supported at launch, within driver control panel
- "now sampling to partners" as of July 2021
- Intel is looking for 3rd party partners to develop custom designs
Intel Battlemage Architecture
- Release Date: Not before 2023
- Discrete GPU architecture
- Successor to "Alchemist" architecture
- Also called "Xe2 HPG"
Intel Celestial Architecture
- Release Date: Not before 2024
- Discrete GPU architecture
- Successor to "Battlemage" architecture
- Also called "Xe3 HPG"
Intel Druid Architecture
- Release Date: Not before 2025
- Discrete GPU architecture
- Successor to "Celestial" architecture
- Also called "Xe Next HPG"
Intel Ponte Vecchio
- Release Date: 2022
- Discrete GPU
- Mix of various manufacturing technologies: Intel 10 nm SuperFin, TSMC 7 nm and TSMC 5 nm
- Multiple GPU dies will be combined into a single accelerator
- Architected "for HPC modeling and simulation workloads and AI training"
- Workloads can be processed by GPU and CPU at the same time, using Intel oneAPI
- Foveros packaging technology
- Supports DirectX 12 mesh shaders
- "petaflops in your palm"
- Will be installed in Leibniz Supercomputing Centre in 2022
- Up to 600 W, liquid-cooled in OAM Form Factor
- Xe link to combine multiple GPUs (CXL interconnect)
- Up to 47 silicon tiles combined to form one big chip
- Eight GPU tiles with 32,768 shader cores each, for a total of 262,144 cores
- Supports ray tracing
- PCI-Express 5.0 interface
- HBM included for each tile
- Hardware acceleration for matrix operations
Zhaoxin Discrete GPU
- Release Date: unknown
- Discrete GPU
- Produced on 28 nanometer production process
- 70 W TDP
- Based on VIA S3 graphics IP
Chipsets
Intel H670, B660 & H610 [updated]
- Release Date: Q1 2022
- Chipset for Alder Lake-S
- More affordable than Z690
- Socket LGA1700
- Possibly no support for PCI-Express 5.0 on B660
Intel W790
- Release Date: Q2 2022
- Chipset for HEDT platform based on Sapphire Rapids
Memory
DDR6 System Memory [added]
- Release Date: Unknown
- Four channels per module (2x that of DDR5, 4x that of DDR4)
- 64 banks
- Speeds starting at 12800 MT/s, up to 17,000 MT/s with OC
GDDR6+ Graphics Memory [added]
- Release Date: Unknown
- Production: 2021
- Up to 24,000 MT/s
- Production process: 1z nm
GDDR7 Graphics Memory [added]
- Release Date: Unknown
- Speeds: 32,000 MT/s
- "Real-time error protection feature", maybe some kind of ECC?
HBM3 Graphics Memory
- Release Date: 2021
- Double the memory bandwidth per stack (4000 Gbps expected)
- Expected to be produced using 7 nm technologies
- Hynix in Oct 2021: 6.4 Gbps per pin, stack bandwidth 819 GB/s, 24 GB and 16 GB stacks
- Rambus announced in August 2021 that their memory controller is ready, up to 8.4 Gbps
- 1024-bit bus width
HBMNext Memory
- Release Date: late 2022 or 2023
- JEDEC work in progress
- Micron involved
Silicon Fabrication Tech
TSMC 6 nanometer
- Release Date: 2021 (Apple)
- Backwards compatible with 7 nm process—no new design tools needed
- Uses EUV (Extreme Ultra Violet), up to four EUV layers
- 18% higher logic density than N7
TSMC 5 nanometer
- Release Date: March 2020 to tape-out customer designs
- Risk production as of Q2 2019
- High volume production: Q2 2020
- Uses TSMC's second implementation of EUV (Extreme Ultra Violet)
- Up to 1.8x the density of 7 nm
- Up to 14 layers
- +15% higher clocks
- 30% better bower than N7
- Intel might be a customer of this node
- N5P "Plus" node: improvement to N5 while staying on 5 nm, 84%–87% increase in transistor densities over N7
TSMC 5 nanometer+
- Release Date: 2021
- High-volume production in Q4 2020
- Uses EUV (Extreme Ultra Violet)
TSMC 4 nanometer
- Volume production: Q3 2021
- Mass production: 2022 or 2023
- Codename "N4"
- Uses EUV lithography
TSMC 4 nanometer+ [added]
- First tape outs: H2 2022
- Codename "N4P"
- 11% performance boost over N5, 6% over N4
- 22% better power vs N5
- 6% higher density than N5
TSMC 3 nanometer [updated]
- April 2020: on track
- Risk production: H2 2021
- Volume production: H2 2022
- FinFET technology
- Uses TSMC's third implementation of EUV (Extreme Ultra Violet)
- 10%–15% speed improvement at iso-power or 25%–30% power reduction at iso-speed, compared to N5
- 30,000 wafers per month at the start, 105,000 by 2023
- 12-inch wafer size
- Intel has announced they have placed two orders for processors based on this process
- AMD will use this process for Zen 4
TSMC 3 nanometer+
- Release date: 2023
- First client will be Apple
TSMC 2 nanometer
- Release Date: 2023 (risk production)
- June 2020: TSMC is accelerating R&D
- Sep 2020: fab construction has begun
- Will use Gate-All-Around (GAA) technology
- Multi-bridge channel field effect transistor (MBCFET) architecture
TSMC 1 nanometer
- Release Date: Unknown
- Uses Semi-metal bismuth for contact electrodes
Samsung 6 nanometer
- Release Date: unknown
- First product taped out as of Q2 2019
- Uses EUV (Extreme Ultra Violet)
- Special variant for customers
Samsung 5 nanometer
- Release Date: 2021
- Ready for customer sample production as of Q2 2019
- In production as of Q4 2020
- Yields are challenging as of Q2 2020
- Yields below 50% as of Q3 2021
- Plans to build fab in Austin TX, for $18B
- Uses EUV (Extreme Ultra Violet)
- Up to 25% the density of 7 nm
- 20% lower power consumption
- 10% higher performance
Samsung 3 nanometer
- Mass Production: H12022
- Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFETTM)
- 50% less power while delivering 30% more performance
- 35% less silicon space taken per transistor (vs. 7 nm)
- 2nd generation 3 nm expected in 2025
Samsung 2 nanometer
- In early development as of Oct 2021, mass production in 2025
- Uses Multi-Bridge-Channel FET (MBCFETTM)
Intel 7 nanometer / "Intel 4"
- Release Date: 2022
- Uses EUV (Extreme Ultra Violet)
- 4x reduction in design rules
- Planned to be used on multiple products: CPU, GPU, AI, FPGA, 5G networking
- 20% perf/watt over 10 nm SuperFin ("Intel 7")
- Jan 2021: Intel reports "issues fixed"
- Jul 2021: Intel renames this process to "Intel 4"
Intel 3
- Release Date: 2023
- Uses EUV (Extreme Ultra Violet)
- Possibly still a 7 nanometer node, with improvements
- 18% perf/watt vs Intel 4
- Denser HP library
- more EUV
- Improve drive-current and via resistance
Intel 20A
- Release Date: H1 2024
- 20 Angstrom = 2 nanometer
- New transistors called RibbonFET
- PowerVia to connect silicon dies
Other
PCI-Express 5.0 SSDs
- Release Date: Phison H2-2022, Kioxia Q4-2021
- Uses new PCIe 5.0 interface to double transfer rates per lane, up to 16 GB/s
- Kioxia: U.2 and M.2 support, up to 14 GB/s
- Phison: E26 controller, PCIe dual port, SR-IOV, ONFI 5.x, ARM R5 CPU 12 nm
- Probably targeted more at enterprise (Intel Sapphire Rapids) than consumer (Intel Alder Lake)
Hynix 4D NAND
- Release Date: H1 2019
- Developed by SK Hynix
- Sampling in Q4 2018
- Products demonstrated at CES 2020: Platinum P31 M.2 NVMe and Gold P31—PCIe 3.0 x4, using flash, DRAM, and controller made by Hynix, over 3 GB/s read/write.
- Reduces chip physical size while increasing capacity
- Supports TLC and QLC
- 30% higher write and 25% higher read performance
- 1.2 V
- 1st generation: 96 stacks, 1.2 Gbps per pin, 512 Gbit TLC
- 128 stacks in development, scales up to 512 stacks
Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC)
- Release Date: Delayed to 2025
- Stores an additional bit of information per cell (compared to QLC)
- 32 states per cell
- Will enable even cheaper SSDs, probably at a performance cost
Toshiba XL-Flash
- Developed by Toshiba
- Uses existing SLC flash technology to improve latencies
- 1/10th the read latency of TLC
- Good for random IOPS and better QoS at shallow queue depth
- Can combine SLC and TLC/QLC for tiered, cost-optimized storage
- Intel Optane memory competitor
- 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
- 4 KB page size for more efficient operating system reads and writes
- 16-plane architecture for more efficient parallelism
- Fast page read and program times
Hynix 176-layer 3D NAND Flash
- Release Date: 2020
- 512 Gbit TLC
- 20% faster read speed per cell
- 1600 MT/s transfer rate
Toshiba 128-layer 3D NAND Flash
- Release Date: 2020 or 2021
- Developed by Toshiba and partner Western Digital
- Called BiCS 5
- According to a press release in Feb 2020, this is actually a 112 layer stacking process
- Cells are TLC (not QLC)
- Chip density: 512 Gb
- Write performance per channel doubled to 133 MB/s
Toshiba 162-layer 3D NAND Flash
- Release Date: 2021
- Developed by Toshiba and partner Western Digital
- Called "6th generation"
- 10% better lateral cell array density
- 40% reduction in die size compared to 112-layer technology
- 10% improvement to read latency
- Uses Circuit Under Array CMOS placement and 4-plane operation
- Reduces cost per bit by 70%
Samsung 176-layer 3D NAND Flash
- Release Date: 2021
- 7th generation V-NAND
- Originally known as "160"-layer 3D NAND, now 176-layer
- Will be used on PCIe 4.0 and 5.0 SSDs
Intel CXL Interconnect
- New interconnect for high-bandwidth devices like GPUs
- Targeted at enterprise and servers
- Competitor to NVLink, Infinity Fabric, and PCI-Express
- Uses PCIe physical layer
- Link layer designed for low latency
- 32 Gbps per lane, per direction (like PCIe Gen 5.0)
- Samsung has announced open-source Scalable Memory Development Kit (SMDK) in Oct 2021
PCI-Express 6.0
- Release Date: 2022
- Spec version 0.9 published as of Oct 2021
- Spec version 0.5 published as of Feb 2020
- Spec version 0.7 published as of Nov 2020
- 64 GT/s raw bit rate, up to 256 GB/s with x16
- Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Maintains backwards compatibility with all previous generations of PCIe technology
- New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
USB 4.0
- Release Date: end of 2020
- Specification Released: September 2019
- Conceptually similar to Thunderbolt 3
- Up to 40 Gbps speeds using two-lane operation
- Multiple data and display protocols can share bandwidth
- Uses USB Type-C connector
- Backwards compatible with USB 2.0, 3.0, 3.1, 3.2, and Thunderbolt 3
- Resulting connection scales to the best mutual capability of the devices being connected
Thunderbolt 5
- Release Date: unknown
- Speeds up to 80 Gbps
- Uses PAM-3 technology for higher transfer rates
- Test chip manufactured on 6 nm at TSMC