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Upcoming Hardware Launches 2024 (Updated Jul 2024)
(407 Comments) »Introduction
In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.
Last Update (Jul 19th):
- Updated AMD Ryzen 5000 XT
- Updated AMD Zen 5 / Ryzen 9000 Series
- Updated Intel Bartlett Lake-S
- Updated Intel Arrow Lake
- Added Intel Arrow Lake Refresh
- Updated Intel Lunar Lake
- Updated Intel Panther Lake
- Updated NVIDIA Blackwell / GeForce RTX 50
- Updated AMD Radeon RX 7700 Non-XT
- Updated AMD Radeon RX 7800 Non-XT
- Added AMD Radeon RX 7900 Non-XT
- Updated Intel Battlemage Architecture
- Updated AMD X870 / B850 / B450 Chipsets
- Updated Intel 800-Series Chipsets
- Added HBM4e Memory
- Updated Samsung 1.4 nanometer
- Updated Intel CXL Interconnect
Processors
AMD Ryzen 5000 XT [updated]
- Release Date: July 2024 #
- Ryzen 9 5900XT: 16c/32t, 4.8 GHz boost, 105 W, $360 #
- Ryzen 7 5800XT: 8c/16t, 4.8 GHz boost, 105 W, $260 #
- Running on Socket AM4 #
AMD Zen 5 / Ryzen 9000 Series [updated]
- Release Date: Jul 31 2024 #
- 5 nm or 3 nm TSMC process
- DDR5 memory support
- PCI-Express Gen 5
- Codename "Granite Ridge" #
- 16 Zen 5 cores across up to two CCDs #
- Strix Point is a hybrid processor, using Zen 5 and Zen 5c cores #
- P-Cores and E-Cores use same instructions and everything, just different cache sizes and clocks #
- Strix Point has 12 MB L2, 24 MB L3, 16 CUs, but only PCIe Gen 4 #
- "Strix Halo" is a mobile SoC with 16 Zen 5 cores, 40 CU GPU, 256-bit LPDDR5X memory, PCI Gen 4, 120 W TDP #
- Strix Halo: BGA package FP11, 37.5 x 45 mm. 1 or 2 Zen 5 CCDs same as Granite Ridge, much larger IO die #
- 256-bit LPDDR5X on Strix Halo #
- Strix Halo uses a different IO die #
- Fire Range is a 16 core successor to Dragon Range using Zen 5 with X3D cache #
- Strix Point IGP is based on RDNA 3.5 architecture #
- 16 CUs in IGP #
- Server platform codename "Turin"
- Server platform memory speed rated at DDR5-6000 #
- CCD codename: Eldora #
- CCD produced in 4 nm TSMC, 70.6 mm² die size and 8.315 billion transistors #
- Core codename: Nirvana #
- Uses Socket SP5 for server, desktop uses Socket AM5
- Die size 224 mm² #
- Shrink to 3 nm possible later in the lifetime of the product
- Could also be built on 3 nm TSMC #
- 3DV Cache included with specific SKUs
- New frontend with better parallelism
- All processors come with integrated GPU
- Improved branch predictor #
- Estimated IPC gain 15% #
- AMD confirms that Ryzen 9000 won't beat 7000X3D at gaming #
- Pipeline redesign: 6 ALUs vs 4 on Zen 4, 4 Address Generation Units (AGUs) vs 3 on Zen 4, floating point store pipelines doubled, now 256-bit each. #
- Performance estimate puts Zen 5 30% ahead of Zen 4 #
- Possibly same IO die as Zen 4 Ryzen 7000 #
- AI/ML enhancements, possibly Xilinx IP-based fixed function hardware, called AIE (AI inference accelerator)
- New AVX and AVX-512 instructions: AVX-VNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI #
- Phoenix point is built on 5 nm TSMC, with RDNA 3 graphics
- Mobile CPU: Kraken Point: 4P+4C cores, NPU, monolithic CPU, 4 nm TSMC EUV, IGP is RDNA 3.5 with 8 CU / 512 cores #
- Related: XDNA, which is the first AI-acceleration FPGA architecture by Xilinx
- 512-bit FPU #
- Ryzen 9000 AM5 CPU looks exactly the same as Ryzen 7000 AM5 #
- Ryzen 9 9950X: 16c/32t, 5.7 GHz, 64 MB L3, 170 W #
- Ryzen 9 9900X: 12c/24t, 5.6 GHz, 64 MB L3, 120 W #
- Ryzen 7 9700X: 8c/16t, 5.5 GHz, 32 MB L3, 65 W #
- Ryzen 5 9600X: 6c/12t, 5.4 GHz, 32 MB L3, 65 W #
- XDNA2 is a next-generation on-chip neural processing architecture #
- Family ID of 26h #
- No support for Windows 10, only Windows 11 #
- Possibly new naming scheme "Ryzen AI 9 HX170" #
- Strix Point could be called "Ryzen 8050 Series" #
- Strix Point: TSMC 4 nm, 232.5 mm², 4x Zen 5 + 8x Zen 5c, 12 MB L2, 24 MB L3 #
- Ryzen AI 9 HX 375: 4x Zen 5 + 8x Zen 5c, Ryzen AI 9 365: 4x Zen 5 + 6x Zen 5c #
- Ryzen 9 9900X Geekbench 6: 3401 single core, 19756 multicore #
- Ryzen 9000X3D uses same 64 MB 3D V-Cache, but has overclocking support #
- Ryzen 9 9950X3D: 16 cores, 128 MB L3, Ryzen 9 9900X3D: 12 cores, 128 MB L3, Ryzen 7 9800X3D 96 MB L3 #
- Models for business use: Ryzen AI 9 HX Pro 370, Ryzen AI 7 Pro 360 #
- Memory speeds up to DDR5-8000, but with 1:2 ratio. Sweetspot around 6000 or 6400 MT/s 1:1 #
- New overclocking method "Curve Shaper" #
AMD Zen 5 Threadripper / Threadripper 9000
AMD Zen 5c
- Release date: Unknown
- 16 cores per CCD, in a single CCX that shares 32 MB L3 cache #
- Produced on a more advanced 3 nm node than Zen 5 #
AMD Zen 6
- Release date: Unknown
- Codename: Morpheus #
- Codename: Sound Wave #
- Codename: Medusa #
- 10% IPC increase over Zen 5 #
- New FP16 capabilities #
- 32-core CCD #
- Not sure if one CCX or two 16-core CCX's #
- Server codename: Venice #
- EPYC uses Socket SP7 #
Intel Bartlett Lake-S [updated]
- Release Date: Q3-2025 #
- Uses Socket LGA 1700 #
- Product by the "Network and Edge" Business group (NEX), so maybe not designed for consumers #
- Uses Intel 7 process #
- Support for DDR4 and DDR5 #
- Could be launched as "15th Gen" #
- UHD Graphics 770 integrated graphics #
- Up to 12 P-Cores, no E-Cores #
- TDPs of 125 W, 65 W and 45 W #
- Core 9: 12P, Core 7: 10P, Core 5: 8P, no Core 3 #
Intel Grand Ridge
- Release Date: Unknown, could be canceled
- Produced on 7 nm HLL+ process
- Successor to Atom "Snow Ridge"
- 24 cores across 6 clusters with 4 cores each
- 4 MB L2 per cluster, plus L3 cache
- Uses Gracemont CPU core
- Dual-channel DDR5
- PCI-Express Gen 4 with 16 lanes
Intel Arrow Lake [updated]
- Release Date: October 2024 #
- Successor to "Meteor Lake"
- Uses Lion Cove P-Core architecture #
- Uses Skymont E-Core architecture #
- Core counts up to 8P+16E
- P-Cores get a performance uplift
- Same E-Cores as Meteor Lake
- Possibly no Hyper-Threading #
- Built on Intel 20A process
- 3 MB L2 cache for each P-Core #
- Graphics tile built on TSMC 3 nanometer N3 #
- Uses Socket LGA1851, retains cooler compatibility with LGA1700 #
- Arrow Lake HX (ARL-HX, for mobile) uses BGA2114 #
- Leaked engineering sample: 8+16+1 core / 24 thread configuration, no Hyper-Threading, 3 GHz, No AVX512 #
- New CPU voltage regulator standard "Gen 5 VR" #
- 6% to 21% faster than Raptor Lake-S #
- New instructions for AI, AVX VNNI with INT8/INT16, AVX-IFMA and AVX-NE Convert. SHA512, SM3 and SM4 #
- Uses Z890, B860 and H810 chipsets, H870 canceled #
- DDR5 up to 6400 officially, higher with OC #
- No support for DDR4 #
- Native Thunderbolt 4 #
- Arrow-Lake-S Desktop SKUs have 4 Xe Core iGPU, no Island Cores #
- 24 native PCIe 5.0 lanes: 16 for graphics, 4x Gen 5 for M.2, 4x Gen 4 for M.2 #
- Another leak suggests 2x M.2 at Gen 5 native x4 #
- Core Ultra 200 branding #
- Core Ultra 9 285K: 8P+16E, 5.5 GHz Boost, 125 W #
- Core Ultra 9 275: 8P+16E, 65 W #
- Core Ultra 7 265K: 8P+12E, 125 W #
- Core Ultra 7 255: 8P+12E, 65 W #
- Core Ultra 5 245K: 6P+8E, 125 W #
- Core Ultra 5 240/F: 6P+4E, 65 W #
- Possible Xe Core configs: 4x Xe, 3x Xe, 2x Xe or 0x Xe #
- Two different dies available: B0 and C0 (smaller) #
- Possibly no integrated NPU in desktop CPUs (Arrow Lake-S) #
- Engineering sample performance: 25% faster than 13900K in CPU-Z 1T, but falls behind in nT #
- P-Cores and E-Cores will be rearranged on the ringbus #
- Gaming laptops could use Arrow Lake-S desktop CPUs, with up to 24 cores #
Intel Arrow Lake Refresh [added]
- Release Date: Unknown
- Adds NPU inside SOC tile #
Intel Lunar Lake [updated]
- Release Date: September 2024 #
- Big tech article here: #
- Lunar Lake MX expected for September 2024 #
- Low power successor to Meteor Lake (U-segment and H-Segment) #
- Core Ultra 2-series branding #
- Live Demo shown at Intel InnovatiON event in Sep 2023 #
- Uses Intel 18A process paired with external foundry services #
- GPU tile on TSMC 3 nanometer N3B #
- Lunar Lake Mobile (LNL-M) uses BGA2833 #
- 15 W ultra-low power CPUs #
- Design focus on performance per watt #
- Improvements to power conversion with help from Cirrus Logic #
- New instructions for AI, AVX VNNI with INT8/INT16, AVX-IFMA and AVX-NE Convert. SHA512, SM3 and SM4 (same as Arrow Lake) #
- Adds Total Storage Encryption (TSE) and PBNDKB instruction #
- Leaked low-power configuration: 17 W, 4+4, 20c 3.91 GHz + 2.61 GHz, 5M, 3.3 GHz IMC, 4x 2.5 MB + 4 MB L2, 2x 8 MB L3 #
- Lunar Lake-MX embeds 16 GB / 32 GB Samsung LPDDR5X-8533 memory on SoC package #
- Lunar Lake-MX Core Ultra 5-238V has 32 GB LPDDR5X-8533 on the CPU package #
- Lunar Lake-MX package size is 27 x 27.5 mm #
- Lunar Lake-MX is 4P+4E, IGP is Xe²-LPG with 8 Xe cores #
- Core Ultra 9 288V: 30 W, 32 GB, 5.1 GHz #
- Core Ultra 7 268V: 17 W, 32 GB, 5.0 GHz #
- Core Ultra 7 266V: 17 W, 16 GB, 5.0 GHz #
- Core Ultra 7 258V: 17 W, 32 GB, 4.8 GHz #
- Core Ultra 7 256V: 17 W, 16 GB, 4.8 GHz #
- Core Ultra 5 238V: 17 W, 32 GB, 4.7 GHz #
- Core Ultra 5 236V: 17 W, 16 GB, 4.7 GHz #
- Core Ultra 5 228V: 17 W, 32 GB, 4.5 GHz #
- Core Ultra 5 226V: 17 W, 16 GB, 4.5 GHz #
- GPU clocks between 1.85 GHz and 2.05 GHz #
Intel Falcon Shores
- Release Date: 2025 #
- Successor to Ponte Vecchio #
- AI and HPC data center "XPU" #
- Used to be CPU+GPU, now GPU only #
- Ethernet, up to 288 GB of HBM3 at 9.8 TB/s #
- Support for FP8 and FP16 #
- Combines multiple tiles of various architectures #
- Up to 1500 W power draw #
- 5x the perf/watt and 5x more bandwidth than Ponte Vecchio #
- Won't be able to run on OAM 2.0, because that tops out at 1000 W #
Intel Twin Lake
Intel Panther Lake [updated]
- Release Date: H2 2025 or H1 2026 #
- Successor to "Lunar Lake" #
- Branded "Core Ultra 300 series" #
- iGPU features Xe3 "Celestial" graphics architecture #
- AI performance doubled #
- Uses Intel 18A process #
- Doubles the core count over Lunar Lake to 16 cores #
- Multi-tile configuration of 5 tiles. CPU and NPU in "Die 4", Platform control (PCD) in "Die 1", iGPU in "Die 5", two other tiles for structural integrity #
- Uses Xe3 "Celestial" GPU cores #
- PTL-U: 4P+0E+4LP, 4 Xe3 cores, 15 W #
- PTL-H: 4P+8E+4LP, 4 Xe3 cores, 25 W #
- PTL-P: 4P+8E+4LP, 12 Xe3 cores, 25 W #
- Possibly increased memory capacities (above 32 GB) #
Intel Granite Rapids
- Release Date: H2 2024, after Sierra Forest #
- For enterprise / data center #
- Successor to Sapphire Rapids #
- Brand name "Xeon 6" #
- Up to 120 Redwood Cove P-Cores (same cores as Meteor Lake) #
- Granite Rapids AP supports up to 2 CPUs, 12 channels DDR5 per CPU, DDR5 6400 MT/s 1 DPC / 5200 MT/s 2 DPC, 24 DIMMs per CPU #
- Another leak suggests up to 128 cores #
- 8-channel DDR5 or more #
- Up to 500 W TDP #
- 88 lanes of PCIe 5.0 #
- BGA4368 package (soldered, not socketed) #
- Socketed Granite Rapids-SP CPUs use LGA 4710 #
- Granite Rapids-AP uses Socket BR with 7529 pins #
- Granite Rapids itself is just the compute die without memory controller for applications like Ethernet. Memory controller dies get added for the HCC (high-core-count) and XCC (extreme core count) variants. HCC has 1 MC with 4 channels, XCC has 2 MC with 8 channels #
- Introduces new AVX10 implementation #
- Support for APX/AVX10 coming to Linux #
- 480 MB of L3 cache #
- Intel 3 node (4 nm) #
- P-Cores only #
- Platform name: Eagle Stream
- Validation platform: Beechnut City #
- 32 DIMMs in 16-channel config #
- Granite-Rapids AP platform: Birch Stream-AP #
- Xeon 6 6980P: 128 cores, 2.0-3.2 GHz, 500 W TDP #
- Xeon 6 6979P: 120 cores, 2.1-3.2 GHz, 500 W TDP #
- Xeon 6 6972P: 96 cores, 2.4-3.5 GHz, 500 W TDP #
- Xeon 6 6960P: 72 cores, 2.7-3.8 GHz, 500 W TDP #
- 80-core ES has 2.5 GHz max frequency and 672 MB cache with a TDP of 350 W #
Intel Sierra Forest
- Release Date: H1 2024 #
- Sampling as of March 2023 #
- Successor to Sapphire Rapids Xeons #
- For cloud, server and enterprise, high-density, efficiency compute #
- Platform name: Birch Stream #
- Uses Socket LGA-7529 # #
- Up to 500 W TDP #
- 12-channel memory #
- Intel 3 process #
- 144 cores #
- 288 cores in XCC model #
- 228 core model gets a multi-bench Geekbench 6 score of 7,770, which is higher than Xeon Platinum 8480+, but lower than the latter in single-threaded #
- Only E-Cores, no P-Cores #
- E-Cores are "Crestmont" architecture #
- Chiplet based like Meteor Lake #
- 5 tiles: 2x compute, 2x IO + 1 interposer #
- Compute tiles on Intel 3 #
- Each tile has 36 Sierra Glen E-Core clusters, 108 MB shared L3, 6-channel DDR5 #
- Each E-Core cluster features 4 cores with 4 MB L2 shared and one segment of 3 MB L3 #
- No SMT #
- Compute tiles: 578 mm², IO tiles: 241 mm² #
- Xeon 6 6710E: 64 cores, 96 MB L3, 2.4 GHz, 205 W #
- Xeon 6 6731E: 96 cores, 96 MB L3, 2.2 GHz, 250 W #
- Xeon 6 6740E: 96 cores, 96 MB L3, 2.4 GHz, 250 W #
- Xeon 6 67476: 112 cores, 96 MB L3, 2.0 GHz, 250 W #
- Xeon 6 6756E: 128 cores, 96 MB L3, 1.8 GHz, 225 W #
- Xeon 6 6766E: 144 cores, 108 MB L3, 1.9 GHz, 250 W #
- Xeon 6 6780E: 144 cores, 108 MB L3, 2.2 GHz, 330 W #
Intel Clearwater Forest
- Release Date: 2025 #
- Intel 18A process #
- Could utilize Direct 3D Stacking technology #
- Possibly 288 E-Cores #
Intel Nova Lake
NVIDIA Arm CPUs for Desktop
- Release Date: 2025
- NVIDIA plans to build Arm processors for use in desktop computers #
- Microsoft Windows operating system is supported #
Graphics / GPUs
NVIDIA Blackwell / GeForce RTX 50 [updated]
- Release Date: Q4 2024 # #
- B200 and GB200 announced at GTC 2024 #
- RTX 5090 in 2024, other SKUs will launch in 2025 #
- GB202: 24,576 cores, 12 GPC, 8 TPC per GPC, 512-bit, 32/64 GB GDDR7 #
- GB203: 10,752 cores, 7 GPC, 6 TPC per GPC, 256-bit, 16/32 GB GDDR7 #
- GB205: 6,400 cores, 5 GPC, 5 TPC per GPC, 192-bit, 12 GB GDDR7 #
- GB206: 6,144 cores, 3 GPC, 6 TPC per GPC, 128-bit, 8/16 GB GDDR7 #
- GB207: 2,560 cores, 2 GPC, 5 TPC per GPC, 128-bit, 8/16 GB GDDR6 #
- No GB204 #
- Also just "B100" #
- 512-bit memory interface on flagship GPU #
- GDDR7 memory on top Blackwell GPUs #
- Uses TSMC 3 nm process #
- GeForce 50 chips could use TSMC 5 nm process called "4N" #
- GB100 could be an MCM design #
- GB203 uses 256-bit memory interface #
- NVIDIA is testing designs with power ranges of 250 to 600 W #
- RTX 5090 uses the huge cooler that we saw in leaks for RTX 4090 Ti #
- Micron presentation suggests that RTX 5090 is +42% faster than RTX 4090 #
- B100: $30,000+ per chip, GB200 $60-$70k per unit #
NVIDIA Rubin
- Release Date: Q4 2025 #
- Successor to "Blackwell" #
- Named after the scientist Vera Rubin #
- Flagship GPU: R100, built on TSMC 3 nm EUV, chiplet design, CoWoS-L with HBM4 #
- Grace Ruben GR200 could be 3 nm #
AMD Radeon RX 7500 XT
- Release date: unknown
- Uses Navi 33 GPU #
AMD Radeon RX 7600 XT 10 GB and 12 GB
- Release date: unknown
- PowerColor has registered such models with the EEC #
AMD Radeon RX 7700 Non-XT [updated]
AMD Radeon RX 7800 Non-XT [updated]
AMD Radeon RX 7900 Non-XT [added]
- Release date: unknown
- Acer filed some product names #
AMD Radeon RX 7950 XT / XTX
- Release date: unknown
- Uses Navi 31 GPU #
AMD RDNA 4 / Radeon RX 8000 Series
- Release Date: H2 2024, probably Computex #
- Uses Navi 4x GPU family
- Focus on gaming performance, without going overboard with AI #
- Improvements to draw calls #
- Possibly no plans for high-end GPUs, only x700 and below #
- New ray tracing engine #
- Product stack tops out at $400, but with performance similar to RX 7900 XTX #
- Only Navi 44 and Navi 43 planned #
- Generation codename "GFX1200" # #
- also "GFX1201" #
- Uses 16 Gbps GDDR6 memory #
- Navi 48 XTX ES spotted #
AMD Navi 4c
- Release Date: Possibly canceled #
- Embraces chiplet design even more #
- Separate dies for Shader Engines (SED) and Multimedia & IO (MID) #
- Shader Engine Dies could be built on 3 nanometer TSMC #
- Uses an active interposer (AID) #
AMD RDNA 5
AMD CDNA 3
- Release Date: 2023
- GPU compute focused architecture
- Combined x86 CPU cores with GPU compute units
- 5 nm TSMC process for compute dies
- 6 nm IO die
- Infinity Cache
- Unified memory between CPU and GPU
- Up to 5x higher AI performance per watt than CDNA2
- HBM memory
- Up to 8 silicon dies linked together
- MI300 accelerator taped out by Jun 2022, first silicon in Q3
- APU design (combines GPU dies, core-logic and CPU CCDs into one package)
Intel Alchemist+ Architecture
- Release Date: 2023, probably H2 # #
- Seems to be canceled, considering it's 2024 and Intel is starting to talk about Battlemage #
- Refreshed "Alchemist" architecture #
- Could be on an improved node, better than TSMC 6 nm #
- Possibly higher core speeds with same core counts #
Intel Battlemage Architecture [updated]
- Release Date: possibly before Black Friday 2024 #
- Successor to "Alchemist" #
- New architecture #
- Newer foundry node and higher performance #
- Two variants: "Xe2 HPG" (high-performance) and "Xe2 LPG" (low-power) #
- BMG-21 GPU, also BMG-10 #
- Xe2 LPG will be first used in Meteor Lake IGP #
- Possibly only for desktop and workstation, no add-in cards for mobile #
- Xe core count doubled to 64, or 1024 EUs #
- Another leak suggests 56 Xe cores or 448 EUs #
- Clocks up to 3 GHz #
- IPC improvements and new math formats #
- 256-bit memory, high mem clock #
- Another leak suggests 192-bit memory #
- GPU codename: BMG-G10 # #
- Uses soldered BGA2362 #
- Two variants: BGA2362-BMG-X2 and BGA2727-BMG-X3 #
- Updated Display Engine with UHBR13.5 #
- PCI-Express 5.0 #
- Fabricated on TSMC 4 nm EUV process # # #
Intel Celestial Architecture
- Release Date: H2 2026 #
- Confirmed "in development" as of Jan 2024 #
- Discrete GPU architecture
- Successor to "Battlemage" architecture
- Also called "Xe3 HPG"
- Fabricated on TSMC N3X (3 nm) # #
- Targets "Ultra Enthusiast" segment
- 8192 shaders, 2x that of A770 #
Intel Druid Architecture
- Release Date: Not before 2027
- Discrete GPU architecture
- Successor to "Celestial" architecture
- Also called "Xe Next HPG"
Chipsets
AMD X690E Chipset
- Release Date: Probably 2024 or canceled
- Could be some workstation-focused variant of the X670E chipset #
- Used on ASUS Pro WS X690E-SAGE SE #
AMD X870E Chipset
- Release Date: 2024 #
- Supports Ryzen 9000 Granite Ridge with the Zen 5 architecture #
- Same Socket AM5 as on Ryzen 7000 #
- USB4 40 Gbps support required, which makes this a 3-chip solution (2x Promontory 21 + 1x ASMedia ASM4242) #
- Possibly support for DDR5-8000 EXPO #
AMD X870 / B850 / B450 Chipsets [updated]
- Release Date: 2024 #
- "X870" is the new "B650E" #
- Supports Ryzen 9000 Granite Ridge with the Zen 5 architecture #
- Same Socket AM5 as on Ryzen 7000 #
Intel 800-Series Chipsets [updated]
- Release Date: 2024 #
- Chipset for Arrow Lake CPUs #
- Chipset models: Z890, W880, Q870, B860, H810 #
- H870 canceled #
- All chipsets except for H810 have 1x x16 Gen 5 for GPU + 1x x4 Gen 5 for M.2 #
- Lanes can be split into 2x x8 or 1x x8 + 3x 4 on Q870, Z890, W880
- ECC support on W880 only #
- No memory OC on H810, Q870 #
Memory
DDR6 System Memory
- Release Date: Unknown
- Initial Draft from JEDEC: 2024 #
- Version 1.0 spec: mid-2025 #
- Four channels per module (2x that of DDR5, 4x that of DDR4) #
- 64 banks #
- Speeds starting at DDR6-8800 up to DDR6-17600 in 1st generation #
- LPDDR6 starts at LPDDR6-10667 with 24-bit channel with 2x 12-bit sub-channels #
- Maximum LPDDR6 data rate is expected to be LPDDR6-14400 #
GDDR6W Graphics Memory
- Release Date: Unknown
- Builds on Samsung's Fan-Out Wafer-Level Packaging (FOWLP) technology
- Mounts the silicon memory dies on a wafer instead of a PCB
- Up to 22 Gbps per pin
- With a 512 bit interface that would be 1.4 TB/s
- Up to 24,000 MT/s
- Could be renamed GDDR6+
GDDR7 Graphics Memory
- Release Date: H1 2024 #
- Mass production (Hynix): Q1 2025 #
- JEDEC standard published as of Mar 2024 #
- Speeds: 36,000 MT/s #
- First gen achieves 32 Gbps at 1.2 V, which is lower than the 1.35 V on GDDR6 #
- Over time up to 50,000 MT/s #
- Uses PAM3 signalling # #
- "Real-time error protection feature," maybe some kind of ECC? #
- Improved power efficiency #
- Will be used by NVIDIA GeForce 50 and AMD RDNA 4
- First products could use slower 16 or 24 Gbit speeds #
- Read clock can be configured to "always running," "disabled," "start with RCK start," "start with read" #
- 1ß production node #
- Samsung uses D1z node, 10-nm class with EUV #
- Samsung: 37 Gbps, 16 Gbit #
- 37 Gbps chip displayed at GTC 2024, 1.1 V #
- Samsung 28 Gbps and 32 Gbps chips are announced as of Mar 2024 #
- Able to issue commands in parallel #
- Micron: 16 and 24 Gbit dies, up to 32 Gbps per pin #
- Hynix: 35.4 Gbps, 16 Gbit #
- First test machines with 40 Gbps available as of Mar 2024 #
HBM3e Memory
- Release Date: H1 2024 for first shipments, bigger volume in H2 #
- Hynix: Volume production as of March 2024 #
- Same as HBM3 but with higher speeds #
- Samsung: up to 9.8 Gbps #
- Samsung will supply $3B worth of HBM3e 12H 36 GB stacks to AMD for CDNA #
- Hynix # #
- NVIDIA GB200 will use 192/384 GB of HBM3e #
HBM4 Memory
- Sampling Date: 2025 #
- Mass production: 2026 # #
- Samsung: Non-conductive film (NCF) assembly and hybrid copper bonding (HCB) #
- 2048-bit interface #
- 6000 MT/s #
- Uses a copper layer as a conductor and oxide insulator instead of regular micro bumps #
- TSMC and Hynix have formed a joint venture to develop HBM4 #
- TSMC will use 12 nm and 5 nm to produce HBM4 #
- TSMC: 12-Hi (48 GB) and 16-Hi (64 GB) stacks #
HBM4e Memory [added]
- Mass production: 2026 #
- SK Hynix development #
- Puts memory controller at the bottom of the memory stack #
Silicon Fabrication Tech
TSMC 2 nanometer
- Release Date: Q4-2024 Risk Production #
- Mass Production in Q2-2025 #
- June 2020: TSMC is accelerating R&D
- Sep 2020: fab construction has begun
- Will use Gate-All-Around (GAA) technology
- Probable VVIP customer: Apple #
- Multi-bridge channel field effect transistor (MBCFET) architecture
- 10-15% speed improvement over N3 at same power, or 25-30% power at same speed
- Several process variants: N2, N2P and N2X
- Not using High-NA EUV #
- Nanosheet transistors
TSMC 1.4 nanometer
TSMC 1 nanometer
- Release Date: around 2030 #
- Fab construction: 2026 #
- Uses Semi-metal bismuth for contact electrodes #
- Chip plan planning has started as of Nov 2022 #
- Codename "A10" #
- Uses High-NA EUV #
Samsung 3 nanometer
- Mass Production: H12022
- "Initial production" started as of Jun 30th 2022
- Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFET)
- 45% less power while delivering 23% more performance
- 35% less silicon space taken per transistor (vs. 7 nm)
- 16% less silicon space taken per transistor (vs. 5 nm)
- 2nd generation 3 nm expected in 2025, reduces power by 50%, improves perf by 30%, reduces area by 35%
- Samsung claims 60-70% yields as of May 2023 #
- In Jul 2023 Samsung claimed 60% yields, and points out that this is better than TSMC #
- According to a newer report, both Samsung and TSMC are struggling with yields for their 3 nm node #
- Trial run of second-generation 3 nm process starting in early 2024 #
Samsung 2 nanometer
- In early development as of Oct 2021, mass production in 2025 or H2 2024 #
- Uses Multi-Bridge-Channel FET (MBCFETTM)
- Feb 2024: order received for AI chips #
- Possibly using backside power delivery #
- Efficiency improved by 25%, performance by 12%, area by 5% #
- Samsung's new Texas fab might be 2 nm #
Samsung 1.4 nanometer [updated]
- In planning as of Oct 2022
- Mass Production: 2027 or 2028 #
- GAA (gate-all-around)
- 2.5D/3D integration
- Micro-bumps
Intel 3
- Release Date: 2023
- Uses EUV (Extreme Ultra Violet)
- Possibly still a 7 nanometer node, with improvements
- 18% perf/watt vs Intel 4
- Denser HP library
- more EUV
- Improve drive-current and via resistance
Intel 20A
- Release Date: H1 2024 #
- 20 Angstrom = 2 nanometers
- New transistors called RibbonFET
- PowerVia to connect silicon dies
- 15% perf/watt improvement over Intel 3 #
Intel 18A
- Release Date: 2025 #
- 18 Angstrom = 1.8 nanometer
- Intel expects to beat TSMC to this milestone #
- Improvements to RibbonFET for higher transistor density #
- 10% perf/watt improvement over Intel 20A #
- Feb 2024: an order for Intel 18A has been placed by Faraday Technology Corp. for an Arm-based SOC #
Intel 14A
- Release Date: Unknown #
- 14 Angstrom = 1.4 nanometer #
- 15% performance per watt over Intel 18A #
- 20% increase in transistor density #
- High-NA extreme ultraviolet (EUV) #
- Also 14A-E process with additional 5% performance boost #
[/spoiler]
Intel 10A
Other
Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC)
- Release Date: Delayed to 2025
- Stores an additional bit of information per cell (compared to QLC)
- 32 states per cell
- Will enable even cheaper SSDs, probably at a performance cost
Toshiba XL-Flash
- Developed by Toshiba
- Uses existing SLC flash technology to improve latencies
- 1/10th the read latency of TLC
- Good for random IOPS and better QoS at shallow queue depth
- Can combine SLC and TLC/QLC for tiered, cost-optimized storage
- Intel Optane memory competitor
- 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
- 4 KB page size for more efficient operating system reads and writes
- 16-plane architecture for more efficient parallelism
- Fast page read and program times
Kioxia / WD 218-layer 3D NAND Flash
- Release Date: 2023 #
- Sampling as of Mar 2023 #
- Uses CMOS directly Bonded to Array technology #
- 1 Tb TLC and QLC #
- Density increased by 50% #
- 3.2 GB/s #
- 20% improvement in write performance and read latency #
Hynix 238-layer 3D NAND Flash
- Release Date: 2023
- Mass production: Jun 2023 #
- 2.4 Gbps #
- 21% lower energy
- 20% higher speeds #
- 512 Gb samples shipping as of Aug 22
- 1 Tb in 2023
- 34% higher manufacturing efficiency #
- Will be used in PCIe 5.0 SSDs #
Hynix 321-layer 3D NAND Flash
- Release Date: H1 2025 #
- Transfer rate increased from 164 MB/s to 194 MB/s #
- 1 Tb capacity with TLC #
- 20 Gbit/mm² #
- 41% more bit growth, 13% shorter read latency, 12% faster program performance, 10% better read power efficiency #
- 16 KB page size, 4 planes #
- 2400 MT/s #
- Made from three stack of 107-layers each #
Micron 232-layer 3D NAND QLC Flash
- Mass Production: April 2024 #
- Used in Micron 2500 SSD #
- 2400 MT/s #
- 24% better read performance, 31% better programming performance #
Samsung 290 layer 3D NAND Flash
- Release Date: 2024 #
- Mass Production started of 1 Tbit TLC: Apr 2024 #
- 9th generation V-NAND #
- 11 nm class process #
Samsung 280-layer 3D NAND QLC Flash
- Release Date: Unknown
- Mass Production for QLC in H2 2024 #
- Density: 1 Tbit #
- Density: 28.5 Gb/mm² at 3.2 GB/s #
Samsung 430-layer 3D NAND Flash
- Release Date: 2025 #
Intel CXL Interconnect [updated]
- New interconnect for high-bandwidth devices like CPUs, GPUs, memory
- Targeted at enterprise and servers
- Competitor to NVLink, Infinity Fabric, and PCI-Express
- Uses PCIe physical layer
- Link layer designed for low latency
- 32 Gbps per lane, per direction (like PCIe Gen 5.0)
- Samsung has announced open-source Scalable Memory Development Kit (SMDK) in Oct 2021
- CXL Memory standardized as of Jun 2024 #
PCI-Express 6.0
- Release Date: 2023
- Hardware expected: 2024
- Spec version 1.0 published as of Jan 2022
- Spec version 0.9 published as of Oct 2021
- Spec version 0.5 published as of Feb 2020
- Spec version 0.7 published as of Nov 2020
- 64 GT/s raw bit rate, up to 256 GB/s with x16
- Rambus has controller IP ready as of Jan 2022
- Rambus has PHY and controller ready as of Oct 2022
- Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Maintains backwards compatibility with all previous generations of PCIe technology
- New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
PCI-Express 7.0
Oct 11th, 2024 02:13 EDT
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