Applied Materials, Inc. (NASDAQ: AMAT) today reported results for its fourth quarter and fiscal year ended Oct. 25, 2026.

Fourth Quarter Results
Applied generated record revenue of $10.41 billion. On a GAAP basis, the company reported gross margin of 50.4 percent, record operating income of $3.66 billion or 35.1 percent of revenue, and earnings per share (EPS) of $3.40. On a non-GAAP basis, the company reported gross margin of 50.6 percent, record operating income of $3.68 billion or 35.3 percent of revenue, and record EPS of $4.16. The company generated record cash from operations of $3.30 billion and distributed $2.42 billion to shareholders through $2.00 billion in share repurchases and $421 million in dividends.

Micron Technology Inc. (Nasdaq: MU), the only U.S.-based manufacturer of memory and storage solutions, today opened a 60,000-square-foot Micron Training Center (MTC) in Boise, a strategic investment to strengthen the skilled talent pipeline, support advanced semiconductor manufacturing and expand education and apprenticeship pathways in Idaho.

Located near Micron's Boise campus, this unique, collaborative training facility accelerates new-hire readiness through an intensive onboarding boot camp and hands-on training in fab operations and manufacturing systems. The center also serves as a site for community college students and career seekers pursuing semiconductor pathways through the College of Western Idaho (CWI).

Building on more than 30 years of collaboration, Applied Materials, Inc. today announced a new innovation partnership with TSMC to accelerate the development and commercialization of semiconductor technologies required for the next era of AI. Working together at Applied's EPIC Center in Silicon Valley, the companies will co-innovate to advance materials engineering, equipment innovation, and process integration technologies designed to deliver energy-efficient performance from the data center to the edge.

"Applied and TSMC share a long history of deep collaboration built on trust and a shared commitment to advancing innovation at the leading edge of semiconductor technology," said Gary Dickerson, President and CEO of Applied Materials. "By bringing our teams together at the EPIC Center, we are strengthening that partnership and accelerating the development of technologies to address the unprecedented complexity driving the chip making roadmap."

Applied Materials, Inc. today announced it is working with Micron Technology to develop next-generation DRAM, high-bandwidth memory (HBM) and NAND solutions that increase the energy-efficient performance of AI systems, bringing together advanced R&D capabilities from Applied's EPIC Center in Silicon Valley and Micron's state-of-the-art innovation center in Boise, Idaho to strengthen the semiconductor innovation pipeline in the United States.

"Applied Materials and Micron have a long-standing partnership focused on driving higher performance and more energy-efficient advanced memory chips by pushing the boundaries of materials engineering and manufacturing innovation," said Gary Dickerson, President and CEO of Applied Materials. "We are excited to deepen our collaboration with Micron as a founding partner at the EPIC Center as next-generation memory technologies play an increasingly vital role in the future of AI systems."

Applied Materials, Inc., the leader in materials engineering for the semiconductor industry, today introduced new deposition, etch and materials modification systems that boost the performance of leading-edge logic chips at 2 nm and beyond. The technologies supercharge AI compute through atomic-scale improvements to the most fundamental electronic building block - the transistor.

The transition to Gate-All-Around (GAA) transistors is a major industry inflection and a critical enabler of the energy-efficient computing needed to deliver more powerful AI chips. As 2 nm-class GAA chips ramp to volume production this year, Applied is introducing new material innovations to enhance next-generation GAA transistors for angstrom nodes. The combined impact of the new chipmaking systems contributes a significant portion of the total energy-efficient performance gains of GAA process node transitions.

Applied Materials, Inc. today introduced new semiconductor manufacturing systems that boost the performance of advanced logic and memory chips foundational to AI computing. The new products target three critical areas in the race to deliver ever more powerful AI chips: leading-edge logic including Gate-All-Around (GAA) transistors, high-performance DRAM including high-bandwidth memory (HBM), and advanced packaging to create highly integrated systems-in-a-package that optimize chip performance, power consumption and cost.

"As chips become more complex, Applied is focused on driving materials engineering breakthroughs to provide the performance and power-efficiency improvements needed to scale AI," said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. "We are collaborating earlier and deeper with our customers to co-develop solutions that accelerate chipmaker roadmaps and enable major device inflections in logic, memory and advanced packaging."

Apple today announced a new $100 billion commitment to America, a significant acceleration of its U.S. investment that now totals $600 billion over the next four years. Today's announcement includes the ambitious new American Manufacturing Program (AMP), dedicated to bringing even more of Apple's supply chain and advanced manufacturing to the U.S. Through AMP, Apple will increase its investment across America and incentivize global companies to manufacture even more critical components in the United States.

"Today, we're proud to increase our investments across the United States to $600 billion over four years and launch our new American Manufacturing Program," said Tim Cook, Apple's CEO. "This includes new and expanded work with 10 companies across America. They produce components that are used in Apple products sold all over the world, and we're grateful to the President for his support."

A recent study by TechInsights is reshaping the narrative around the cost of semiconductor manufacturing in the United States. According to the survey, processing a 300 mm wafer at TSMC's Fab 21 in Phoenix, Arizona, is only about 10% more expensive than similar operations in Taiwan. This insight challenges earlier assumptions based on TSMC founder Morris Chang's comments, which suggested that high fab-building expenses in Arizona made US chip production financially impractical. G. Dan Hutcheson of TechInsights highlighted that the observed cost difference largely reflects the expenses associated with establishing a brand-new facility. "It costs TSMC less than 10% more to process a 300 mm wafer in Arizona than the same wafer made in Taiwan," he explained. The initial higher costs stem from constructing a fab in an unfamiliar market with a new, sometimes unskilled workforce—a scenario not typical for mature manufacturing sites.

A significant portion of the wafer production cost is driven by equipment, which accounts for well over two-thirds of the total expenses. Leading equipment providers like ASML, Applied Materials, and Lam Research charge similar prices globally, effectively neutralizing geographic disparities. Although US labor costs are higher than in Taiwan, the heavy automation in modern fabs means that labor represents less than 2% of the overall cost. Additional logistics for Fab 21, including the return of wafers to Taiwan for dicing, testing, and packaging, add complexity but only minimally affect the overall expense. With plans to expand domestic packaging capabilities, TSMC's approach is proving to be strategically sound. This fresh perspective suggests that the apparent high cost of US fab construction has been exaggerated. TSMC's $100B investment in American semiconductor manufacturing reflects a calculated decision informed by detailed cost analysis—demonstrating that location-based differences become less significant when the equipment dominates expenses.

The Biden administration is set to announce new, targeted restrictions on China's semiconductor industry, focusing primarily on emerging chip manufacturing equipment companies rather than broad industry-wide limitations. According to Bloomberg, these new restrictions are supposed to take effect on Monday. The new rules will specifically target two manufacturing facilities owned by Semiconductor Manufacturing International Corp. (SMIC) and will add select companies to the US Entity List, restricting their access to American technology. However, most of Huawei's suppliers can continue their operations, suggesting a more mild strategy. The restrictions will focus on over 100 emerging Chinese semiconductor equipment manufacturers, many of which receive government funding. These companies are developing tools intended to replace those currently supplied by industry leaders such as ASML, Applied Materials, and Tokyo Electron.

The moderated approach comes after significant lobbying efforts from American semiconductor companies, who argued that stricter restrictions could disadvantage them against international competitors. Major firms like Applied Materials, KLA, and Lam Research voiced concerns about losing market share to companies in Japan and the Netherlands, where similar but less stringent export controls are in place. Notably, Japanese companies like SUMCO are already seeing the revenue impacts of Chinese independence. Lastly, the restrictions will have a limited effect on China's memory chip sector. The new measures will not directly affect ChangXin Memory Technologies (CXMT), a significant Chinese DRAM manufacturer capable of producing high-bandwidth memory for AI applications.

Applied Materials, Inc. today introduced the MAX OLED solution, a patented OLED pixel architecture and revolutionary display manufacturing technology designed to bring the superior OLED displays found in high-end smartphones to tablets, PCs and eventually TVs.

OLED is the display technology of choice for the world's leading smartphone manufacturers because it offers superior display quality, light and flexible form factors, and durability. However, until today, it has proven challenging to scale OLED display manufacturing to the larger glass panels used to make displays for tablets, PCs and TVs.

According to a recent report from Nikkei, China has claimed the number one spot as the single highest spender on chipmaking tools. As the data from SEMI highlights, China spent a whopping $25 billion on key semiconductor tools in the first half of 2024, more than the US, Taiwan, and South Korea combined. And the train of acceleration for the Chinese semiconductor industry doesn't seem to be slowing down, as the country is expected to spend more than $50 billion for the entire year 2024. However, this equipment is not precisely leading-edge, as Chinese companies are under Western sanctions and are unable to source advanced EUV lithography tools for making sub-7 nm chips.

Most of the spending is allocated to mature node chipmaking facilities. These so-called "second tier" companies are driving the massive expenditures, and they are plentiful. Nikkei reports that there are at least ten firms that operate with mature nodes like 10/12/16 nm nodes. Being the biggest spender, China is also one of the primary revenue sources for many companies. For the US chipmaking tool companies like Applied Materials, Lam Research, and KLA, Chinese purchases accounted for 32%, 39%, and 44% of their latest quarterly revenue, respectively. Tokyo Electron recorded orders to China accounting for 49.9% of its revenues in June, while the Netherlands giant ASML also attributed 49%. Perhaps even more interesting is the expected outlook for 2025, which shows no signs of slowing down. The Chinese semiconductor industry must establish complete self-sufficiency, and massive capital expenditures are expected to continue.

Applied Materials, Inc. today introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2 nm logic node and beyond. "The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption," said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. "Applied's newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights."

Overcoming the Physics Challenges of Classic Moore's Law Scaling
Today's most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip's wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry's workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

Applied Materials, Inc. today announced a landmark investment to build the world's largest and most advanced facility for collaborative semiconductor process technology and manufacturing equipment research and development (R&D). The new Equipment and Process Innovation and Commercialization (EPIC) Center is planned as the heart of a high-velocity innovation platform designed to accelerate development and commercialization of the foundational technologies needed by the global semiconductor and computing industries.

To be located at an Applied campus in Silicon Valley, the multibillion-dollar facility is designed to provide a breadth and scale of capabilities that is unique in the industry, including more than 180,000 square feet - more than three American football fields - of state-of-the-art cleanroom for collaborative innovation with chipmakers, universities and ecosystem partners. Designed from the ground up to accelerate the pace of introducing new manufacturing innovations, the new EPIC Center is expected to reduce the time it takes the industry to bring a technology from concept to commercialization by several years, while simultaneously increasing the commercial success rate of new innovations and the return on R&D investments for the entire semiconductor ecosystem.

According to Bloomberg, Japan and the Netherlands are getting ready to join the US in limiting access to advanced semiconductor manufacturing equipment for China. The three nations are currently in talks—that might end as soon as today—over how they can impose joint limits on what kind of equipment and tools can be exported to China. Apparently there will be no official announcement if a deal is struck, instead the restrictions will simply be implemented as required.

Bloomberg states that the Netherlands will expand export restrictions that ASML is already under, which according to the publication means stricter export rules around DEUV machines, which are used in cutting edge semiconductor nodes. Japan is said to implement similar export restrictions for Nikon as well as Tokyo Electron, with the US already having implemented restrictions for Applied Materials. The export restriction deal is in part being done to appease US equipment makers, who have complained that their international competitors haven't been under the same export restrictions when it comes to China, as they have. The question is if the export restrictions will hinder China in the long run, or if the nation will simply push ahead and develop its own, competing semiconductor manufacturing tools.

Update Jan 28th: Japan and the Netherlands reached an agreement with the US on Friday and the two countries are said to be making individual announcements with regards to their individual agreements with the US.

TSMC today held a 3 nanometer (3 nm) Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP), bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the Company's advanced manufacturing.

TSMC has laid a strong foundation for 3 nm technology and capacity expansion, with Fab 18 located in the STSP serving as the Company's GIGAFAB facility producing 5 nm and 3 nm process technology. Today, TSMC announced that 3 nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3 nm technology will create end products with a market value of US$1.5 trillion within five years of volume production.

ASML is one of the critical semiconductors companies, as they provide tools for making actual silicon. Located in the Netherlands, they are famous for their DUV and EUV lithography tools, used to etch designs onto silicon wafers. According to the report from Bloomberg, the United States governing body is negotiating with the Dutch government to restrict the export of ASML's products to China. This came to affection following US Deputy Commerce Secretary Don Graves's visit to the Netherlands to discuss supply chain issues and meeting with ASML Chief Executive Officer Peter Wennink. While these suggested export restrictions could be beneficial to the strategic placement of US against China, it would hurt ASML's revenue as sales in China accounted for a 16% share of the company's revenue in 2021.

It is recorded that the Chinese spending spree on tools has been the greatest among every country, lasting for two years in a row. By banning ASML from exporting its lithography tools to China, the US could theoretically halt Chinese plans for achieving the government's intended semiconductor independence. The talks with the Dutch government and ASML are still a work in progress, so we are yet to see if the deal is finalized. Additionally, it is worth pointing out that the major US semiconductor manufacturing tool makers like Applied Materials and Lam Research are already banned from exporting to China.

Applied Materials, Inc. today unveiled a new way to engineer the wiring of advanced logic chips that enables scaling to the 3 nm node and beyond. While size reduction benefits transistor performance, the opposite is true in the interconnect wiring: smaller wires have greater electrical resistance which reduces performance and increases power consumption. Without a materials engineering breakthrough, interconnect via resistance would increase by a factor of 10 from the 7 nm node to the 3 nm node, negating the benefits of transistor scaling.

Applied Materials has developed a new materials engineering solution called the Endura Copper Barrier Seed IMS. It is an Integrated Materials Solution that combines seven different process technologies in one system under high vacuum: ALD, PVD, CVD, copper reflow, surface treatment, interface engineering and metrology. The combination replaces conformal ALD with selective ALD, eliminating a high-resistivity barrier at the via interface. The solution also includes copper reflow technology that enables void free gap fill in narrow features. Electrical resistance at the via contact interface is reduced by up to 50 percent, improving chip performance and power consumption, and enabling logic scaling to continue to 3 nm and beyond.