Applied Materials, Inc. today announced a landmark investment to build the world's largest and most advanced facility for collaborative semiconductor process technology and manufacturing equipment research and development (R&D). The new Equipment and Process Innovation and Commercialization (EPIC) Center is planned as the heart of a high-velocity innovation platform designed to accelerate development and commercialization of the foundational technologies needed by the global semiconductor and computing industries.

To be located at an Applied campus in Silicon Valley, the multibillion-dollar facility is designed to provide a breadth and scale of capabilities that is unique in the industry, including more than 180,000 square feet - more than three American football fields - of state-of-the-art cleanroom for collaborative innovation with chipmakers, universities and ecosystem partners. Designed from the ground up to accelerate the pace of introducing new manufacturing innovations, the new EPIC Center is expected to reduce the time it takes the industry to bring a technology from concept to commercialization by several years, while simultaneously increasing the commercial success rate of new innovations and the return on R&D investments for the entire semiconductor ecosystem.

According to Bloomberg, Japan and the Netherlands are getting ready to join the US in limiting access to advanced semiconductor manufacturing equipment for China. The three nations are currently in talks—that might end as soon as today—over how they can impose joint limits on what kind of equipment and tools can be exported to China. Apparently there will be no official announcement if a deal is struck, instead the restrictions will simply be implemented as required.

Bloomberg states that the Netherlands will expand export restrictions that ASML is already under, which according to the publication means stricter export rules around DEUV machines, which are used in cutting edge semiconductor nodes. Japan is said to implement similar export restrictions for Nikon as well as Tokyo Electron, with the US already having implemented restrictions for Applied Materials. The export restriction deal is in part being done to appease US equipment makers, who have complained that their international competitors haven't been under the same export restrictions when it comes to China, as they have. The question is if the export restrictions will hinder China in the long run, or if the nation will simply push ahead and develop its own, competing semiconductor manufacturing tools.

Update Jan 28th: Japan and the Netherlands reached an agreement with the US on Friday and the two countries are said to be making individual announcements with regards to their individual agreements with the US.

TSMC today held a 3 nanometer (3 nm) Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP), bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the Company's advanced manufacturing.

TSMC has laid a strong foundation for 3 nm technology and capacity expansion, with Fab 18 located in the STSP serving as the Company's GIGAFAB facility producing 5 nm and 3 nm process technology. Today, TSMC announced that 3 nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3 nm technology will create end products with a market value of US$1.5 trillion within five years of volume production.

ASML is one of the critical semiconductors companies, as they provide tools for making actual silicon. Located in the Netherlands, they are famous for their DUV and EUV lithography tools, used to etch designs onto silicon wafers. According to the report from Bloomberg, the United States governing body is negotiating with the Dutch government to restrict the export of ASML's products to China. This came to affection following US Deputy Commerce Secretary Don Graves's visit to the Netherlands to discuss supply chain issues and meeting with ASML Chief Executive Officer Peter Wennink. While these suggested export restrictions could be beneficial to the strategic placement of US against China, it would hurt ASML's revenue as sales in China accounted for a 16% share of the company's revenue in 2021.

It is recorded that the Chinese spending spree on tools has been the greatest among every country, lasting for two years in a row. By banning ASML from exporting its lithography tools to China, the US could theoretically halt Chinese plans for achieving the government's intended semiconductor independence. The talks with the Dutch government and ASML are still a work in progress, so we are yet to see if the deal is finalized. Additionally, it is worth pointing out that the major US semiconductor manufacturing tool makers like Applied Materials and Lam Research are already banned from exporting to China.

Applied Materials, Inc. today unveiled a new way to engineer the wiring of advanced logic chips that enables scaling to the 3 nm node and beyond. While size reduction benefits transistor performance, the opposite is true in the interconnect wiring: smaller wires have greater electrical resistance which reduces performance and increases power consumption. Without a materials engineering breakthrough, interconnect via resistance would increase by a factor of 10 from the 7 nm node to the 3 nm node, negating the benefits of transistor scaling.

Applied Materials has developed a new materials engineering solution called the Endura Copper Barrier Seed IMS. It is an Integrated Materials Solution that combines seven different process technologies in one system under high vacuum: ALD, PVD, CVD, copper reflow, surface treatment, interface engineering and metrology. The combination replaces conformal ALD with selective ALD, eliminating a high-resistivity barrier at the via interface. The solution also includes copper reflow technology that enables void free gap fill in narrow features. Electrical resistance at the via contact interface is reduced by up to 50 percent, improving chip performance and power consumption, and enabling logic scaling to continue to 3 nm and beyond.