Samsung has reportedly booked the entire planned output of its second fab in Taylor, Texas, and most of it is going to AMD. According to an exclusive from Korea's Maeil Business Newspaper, citing industry sources, Taylor Fab 2 will make HBM base dies for AMD and NVIDIA on a 2 nm process, with AMD's orders making up the bulk of it. Apparently, AMD's volume alone is enough to stretch the fab's capacity. Samsung declined to comment, saying it can't confirm customer-related details.

These aren't AMD's CPUs or GPUs, though. The base die is the logic chip at the bottom of an HBM stack, and Samsung plans to pair the Texas-made dies with DRAM produced in South Korea and ship them as finished HBM. Its current HBM4 and the sampled HBM4E use 4 nm base dies, so 2 nm or smaller seems aimed at later HBM generations. The deal also follows Lisa Su's visit to Samsung in October, where Samsung reportedly wanted foundry orders from AMD in return for the HBM that AMD urgently needs. A March MOU had already made Samsung the primary HBM4 supplier for the Instinct MI455X.

Samsung is reportedly collaborating with the world's largest chip maker, TSMC, to secure a base die supply for NVIDIA's newly announced NVHBM memory standard. NVHBM integrates the controller into the 3D HBM stack, significantly enhancing performance and efficiency. Compared to standard HBM4E, NVIDIA claims up to 30% more memory bandwidth, 15% lower HBM power consumption, and up to 25% more usable compute die area on the processing unit. In simple terms, NVHBM builds on the standard HBM architecture with base die customization, but there are a few strict requirements that must be fulfilled before mass production.

Interestingly, one of the requirements is that NVIDIA's base die in the NVHBM must be manufactured on TSMC's 3 nm node. Even though Samsung has its own 3 nm production lines, NVIDIA's IP is optimized for TSMC's nodes. This forces Samsung to collaborate with TSMC and become a customer, despite having its own production capabilities. However, this arrangement is only for the base die, which integrates directly next to the compute tiles. For memory, Samsung will continue using its sixth-generation 10 nm processes, which are typical for HBM manufacturing. This means that only part of the production will be handled by TSMC.

Samsung's upcoming HBM4E memory has reportedly passed testing for NVIDIA's next-generation "Rubin Ultra" AI GPU accelerator family. This is great news for the company, as its previous HBM3E didn't meet NVIDIA's requirements, leading NVIDIA to choose Samsung for GDDR7 only, instead of HBM3E. The new HBM generation brings significant advancements, and Samsung is one of the leading manufacturers with designs currently running at 14 Gbps per pin and 2,048 pins per HBM4E stack. Samsung can achieve a maximum bandwidth of 3.6 TB/s, and at 16 Gbps, this maximum memory bandwidth will increase to 4 TB/s for a single HBM4E stack.

With about a dozen memory stacks per AI accelerator or GPU, the total memory bandwidth will be remarkable. The company is currently offering this memory in a 12-layer (or 12-high) configuration with a memory density of 48 GB per stack. However, customer requirements will also include 8-layer 32 GB and 16-layer 64 GB stacks in the future.

NVIDIA announced today that it is investing $3.5 billion in MediaTek and adding new layers of collaboration between the two silicon giants. It's important to note that NVIDIA and MediaTek are already working together, as MediaTek designed an SoC called GB10 that powers NVIDIA's RTX Spark consumer products and DGX Spark mini workstations. Both companies have confirmed that they will be approaching the collaboration through NVIDIA's NVLink Fusion ecosystem. NVLink Fusion serves as an IP and chiplet framework that allows non-NVIDIA processors and accelerators to become key participants in the company's data center fabric.

MediaTek will offer the NVLink Fusion platform to its customers, which include numerous ASIC clients like Google, enabling them to connect their XPUs to the NVLink Fusion scale-up fabric using photonic or classical copper interconnects. This includes the NVLink-C2C high-bandwidth fabric, which can connect multiple nearby XPUs and is also used in the upcoming NVIDIA "Rosa" CPUs. Additionally, MediaTek will offer customers NVIDIA's newly announced NVHBM, which integrates the controller into the 3D HBM stack, significantly enhancing performance and efficiency. Compared to standard HBM4E, NVIDIA claims up to 30% more memory bandwidth, 15% lower HBM power consumption, and up to 25% more usable compute die area on the processing unit.