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PCI-SIG Announces PCIe 6.0 Specification

PCI-SIG today announced that PCI Express (PCIe ) 6.0 technology will double the data rate to 64 GT/s while maintaining backwards compatibility with previous generations and delivering power efficiency and cost-effective performance. The PCIe 6.0 specification is actively targeted for release in 2021.

PCIe 6.0 Specification Features
  • Delivers 64 GT/s raw bit rate and up to 256 GB/s via x16 configuration
  • Utilizes PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and leverages existing 56G PAM-4 in the industry
  • Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
  • Maintains backwards compatibility with all previous generations of PCIe technology

PCI SIG Releases PCI-Express Gen 4.0 Specifications

The Peripheral Component Interconnect (PCI) special interest group (SIG) published the first official specification (version 1.0) of PCI-Express gen 4.0 bus. The specification's previous draft 0.9 was under technical review by members of the SIG. The new generation PCIe comes with double the bandwidth of PCI-Express gen 3.0, reduced latency, lane margining, and I/O virtualization capabilities. With the specification published, one can expect end-user products implementing it. PCI SIG has now turned its attention to the even newer PCI-Express gen 5.0 specification, which will be close to ready by mid-2019.

PCI-Express gen 4.0 comes with 16 GT/s bandwidth per-lane, per-direction, which is double that of gen 3.0. An M.2 NVMe drive implementing it, for example, will have 64 Gbps of interface bandwidth at its disposal. The SIG has also been steered toward lowering the latencies of the interconnect as HPC hardware designers are turning toward alternatives such as NVLink and InfinityFabric, not primarily for the bandwidth, but the lower latency. Lane margining is a new feature that allows hardware to maintain a uniform physical layer signal clarity across multiple PCIe devices connected to a common root complex. This is particularly important when you have multiple pieces of mission-critical hardware (such as RAID HBAs or HPC accelerators), and require uniform performance across them. The new specification also adds new I/O virtualization features that should prove useful in HPC and cloud computing.

AMD Unveils World's First Hardware-Based Virtualized GPU Solution at VMworld

AMD today at VMworld 2015 demonstrated the world's first hardware-based GPU virtualization solution, the AMD Multiuser GPU. This new solution from AMD enables a virtualized workstation-class experience with full ISV certifications and local desktop-like performance. With the AMD Multiuser GPU, IT pros can easily configure these solutions to allow up to 15 users on a single AMD GPU. Demonstrations of AMD virtualization solutions can be found at VMworld 2015 booth 447.

"The AMD graphics cards are uniquely equipped with AMD Multiuser GPU technology embedded into the GPU delivering consistent and predictable performance," said Sean Burke, AMD corporate vice president and general manager, Professional Graphics. "When these AMD GPUs are appropriately configured to the needs of an organization, end users get the same access to the GPU no matter their workload. Each user is provided with the virtualized performance to design, create and execute their workflows without any one user tying up the entire GPU."

Built around industry standard SR-IOV (Single Root I/O Virtualization) technology, the AMD Multiuser GPU continues AMD's embracement of non-proprietary open standards. SR-IOV is a specification developed by the PCI SIG, and provides a standardized way for devices to expose hardware virtualization. The AMD Multiuser GPU is designed to preserve and support graphics- and compute-accelerated features for design and manufacturing or media and entertainment applications. The AMD Multiuser GPU addresses limitations of current virtualized GPU solutions that may not provide predictable performance for CAD/CAE, Media and Entertainment, and general enterprise GPU needs.

PCI Takes on Thunderbolt, Big Worries for its Promoters

Did you know what lies behind the USB 3.0 or Thunderbolt controller? It's of course the bus that connects it to the rest of the system, PCI-Express. It is the 500 MB/s per lane interconnect that is indirectly responsible for the awesome bandwidth that today's plug and play interfaces such as eSATA 6 Gb/s, USB 3.0, and Thunderbolt 10 Gb/s enjoy. What if you could eliminate the protocol overhead that comes with any of those protocols, and make PCI-Express directly an interconnect? So thought the PCI Special Interest Group (SIG), the body that decides the fate of PCI. The SIG is planning to create a cabled version of PCI-Express Gen 3, that has no secondary protocol overhead, not even of the kind Infiniband has.

A single PCI-Express 3.0 lane can provide 8 Gbps (1 GB/s) of bandwidth in each direction, the new cabled interconnect can supply bandwidth of four Gen 3 lanes, totaling 32 Gbps, over three times that of the current version of Thunderbolt. Apart from that bandwidth, cabled PCI-E will be designed to supply 20W of power to its devices, plenty of power for even a small 3-bay HDD rack. The connector itself will be designed to be very compact and flat, so it can be fitted into notebooks and tablets. PCI SIG plans to have the first specifications of cabled PCI-Express ready before June 2013. By 2013, Intel will be about 2 years away from releasing its proposed 50 Gbps version of Thunderbolt, but even then, Thunderbolt is an additional protocol that sits over the system bus (again, PCI-Express), unless Intel designs Thunderbolt controllers to somehow talk to CPU over QPI.

PCI SIG Unveils More PCI-Express 3.0 Details

Al Yanes, chairman of the PCI Special Interest Group (SIG) shared on Wednesday some additional details of the next generation PCI-Express 3.0 standard. The PCI-E 3.0 specification will almost double the transfer speed of PCI-E 2.0 at 8GT/s (gigatransfers per second). The good news is that PCI-Express 3.0 will be backwards-compatible with PCI Express 2.0. Since the connector will remain the same, the only difference should be in the electrical specifications. The final specs for the PCI-E 3.0 standard are expeted to be completed in late 2009, while testing is set to start in the second half of 2010. First products that will utilize the new slot will start surfacing some time after that.
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