News Posts matching "PCI-SIG"

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Intel Reveals the "What" and "Why" of CXL Interconnect, its Answer to NVLink

CXL, short for Compute Express Link, is an ambitious new interconnect technology for removable high-bandwidth devices, such as GPU-based compute accelerators, in a data-center environment. It is designed to overcome many of the technical limitations of PCI-Express, the least of which is bandwidth. Intel sensed that its upcoming family of scalable compute accelerators under the Xe band need a specialized interconnect, which Intel wants to push as the next industry standard. The development of CXL is also triggered by compute accelerator majors NVIDIA and AMD already having similar interconnects of their own, NVLink and InfinityFabric, respectively. At a dedicated event dubbed "Interconnect Day 2019," Intel put out a technical presentation that spelled out the nuts and bolts of CXL.

Intel began by describing why the industry needs CXL, and why PCI-Express (PCIe) doesn't suit its use-case. For a client-segment device, PCIe is perfect, since client-segment machines don't have too many devices, too large memory, and the applications don't have a very large memory footprint or scale across multiple machines. PCIe fails big in the data-center, when dealing with multiple bandwidth-hungry devices and vast shared memory pools. Its biggest shortcoming is isolated memory pools for each device, and inefficient access mechanisms. Resource-sharing is almost impossible. Sharing operands and data between multiple devices, such as two GPU accelerators working on a problem, is very inefficient. And lastly, there's latency, lots of it. Latency is the biggest enemy of shared memory pools that span across multiple physical machines. CXL is designed to overcome many of these problems without discarding the best part about PCIe - the simplicity and adaptability of its physical layer.

ASMedia to Continue as Chipset Supplier to AMD, But X570 an In-house Chipset

AMD's socket AM4 and socket TR4 chipsets are originally designed by ASMedia. With its "Zen" family of processors being full-fledged SoCs, the motherboard "chipset" only serves to increase connectivity, and ASMedia already holds certifications for key groups such as the PCI-SIG, USB-IF, SATA-IO, NVM-Express group, etc. It's being reported now that ASMedia will develop some, if not all 500-series chipsets, with the exception of X570. The X570 will be an in-house design by AMD, which will use its own foundry partners (likely GloFo 14 nm) to manufacture it. This presents AMD with an opportunity to harden it against vulnerabilities, and have greater control over pricing, not to mention overcoming key design shortfalls of "Promontory," such as downstream PCIe connectivity.

This flies in the face of speculation that AMD would discontinue ASMedia's supply of chipset, especially in the wake of the "Chimera" vulnerability affecting "Promontory" 300-series and 400-series chipsets. The supposedly security-hardened 500-series chipset will feature PCI-Express gen 4.0 certification. What this means is that the chipset bus between the AM4/TR4 SoC and the chipset will be PCI-Express 4.0 x4 (64 Gbps), translating to double the bandwidth. It remains to be seen if the downstream PCIe lanes put out by the chipset are gen 4.0, too. Current 400-series chipsets continue to put out stale gen 2.0 lanes, compensated for by additional gen 3.0 lanes put out by the SoC. Sources also mention that ASMedia-supplied chipsets will only hit the market toward the end of 2019, which means AMD X570 could be the only 500-series chipset option between the mid-2019 launch of 3rd generation Ryzen, and late-2019. You should be able to run these processors on older socket AM4 motherboards via BIOS updates, though.

SD Express is a New Memory Card Standard That Leverages PCIe and NVMe

The SD Association announced today SD Express which adds the popular PCI Express and NVMe interfaces to the legacy SD interface. The PCIe interface delivering a 985 megabytes per second (MB/s) maximum data transfer rate and the NVMe upper layer protocol enables advanced memory access mechanism, enabling a new world of opportunities for the popular SD memory card. In addition, the maximum storage capacity in SD memory cards grows from 2 TB with SDXC to 128 TB with the new SD Ultra Capacity (SDUC) card. These innovations maintain the SDA's commitment to backward compatibility and are part of the new SD 7.0 specification.

"SD Express' use of popular PCIe and NVMe interfaces to deliver faster transfer speeds is a savvy choice since both protocols are widely used in the industry today and creates a compelling choice for devices of all types," said Mats Larsson, Senior Market Analyst at Futuresource. "The SD Association has a robust ecosystem with a strong history of integrating SD innovations and has earned the trust of consumers around the world."

AMD 400-series Chipset Surfaces on PCI-SIG, PCIe 3.0 General Purpose Confirmed

AMD's second-generation Ryzen processors, which debut some time in Q1-2018, will be accompanied by the company's new 400-series motherboard chipset, even though they are expected to work with existing socket AM4 motherboards based on 300-series chipsets (with BIOS updates). The 400-series Promontory chipset surfaced on the PCIe Integrators List of PCI-SIG, the standards governing body of the PCI bus (which also oversees PCIe specifications development).

The listing seems to confirm that 400-series chipset will feature PCI-Express gen 3.0 general purpose lanes. These are downstream PCIe lanes put out by the chipset, to run the various external onboard controllers on the motherboard, and usually wired to the x1 and x4 PCIe slots. The current 300-series chipset only features up to 8 PCIe gen 2.0 general purpose lanes, and that was seen as a drawback. AMD Ryzen socket AM4 processors put out additional gen 3.0 lanes besides the 16 lanes allocated to PEG (one x16 or two x8, physically x16 slots); and 4 lanes serving as chipset bus. These additional gen 3.0 lanes typically drive a 32 Gb/s M.2 slot. With 400-series chipset bringing gen 3.0 general purpose lanes, one can expect newer socket AM4 motherboards with more than one 32 Gb/s M.2 slot (one from the SoC, another from the chipset).

PCI-SIG: PCIe 4.0 in 2017, PCIe 5.0 in 2019

After years of continued innovation in PCIe's bandwidth, we've hit somewhat of a snag in recent times; after all, the PCIe 3.0 specification has been doing the rounds on our motherboards ever since 2010. PCI-SIG, the 750-member strong organization that's in charge of designing the specifications for the PCIe bus, attribute part of this delay to industry stagnation: PCIe 3.0 has simply been more than enough, bandwidth-wise, for many generations of hardware now. Only recently, with innovations in storage mediums and innovative memory solutions, such as NVMe SSDs and Intel's Optane, are we starting to hit the ceiling on what PCIe 3.0 offers. Add to that the increased workload and bandwidth requirements of the AI field, and the industry now seems to be eager for an upgrade, with some IP vendors even having put out PCIe 4.0-supporting controllers and PHYs into their next-generation products already - although at the incomplete 0.9 revision.
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