JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD330-4: Standard Package High Bandwidth Memory (SPHBM4). SPHBM4 uses the same DRAM dies as HBM4, commonly used in artificial intelligence accelerators, with a new interface base die that enables mounting on standard organic substrates rather than silicon substrates. JESD330-4 is available for download from the JEDEC website.

JESD330-4 SPHBM is architected to operate at the same aggregate data throughput as HBM4 using fewer pins by operating at a higher frequency. Where the HBM4 interface has 2048 data signals, when published, SPHBM4 will define 512 data signals with 4:1 serialization to achieve the same bandwidth. This change allows the relaxed bump pitch required for connection to organic substrates.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced it is nearing completion of a new standard for Standard Package High Bandwidth Memory (SPHBM4). SPHBM4 devices are similar to the HBM4 devices commonly used in artificial intelligence accelerators, using the same DRAM dies on a new interface base die which can be mounted on standard organic substrates. In contrast, HBM4 is typically mounted on silicon substrates.

As planned, SPHBM operates at the same aggregate data throughput as HBM4 using fewer pins by operating at a higher frequency. Where the HBM4 interface has 2048 data signals, when published, SPHBM4 will define 512 data signals with 4:1 serialization to achieve the same bandwidth. This change allows the relaxed bump pitch required for connection to organic substrates.