Infineon Technologies AG today announced that the company has succeeded in developing the world's first 300 mm power gallium nitride (GaN) wafer technology. Infineon is the first company in the world to master this groundbreaking technology in an existing and scalable high-volume manufacturing environment. The breakthrough will help substantially drive the market for GaN-based power semiconductors. Chip production on 300 mm wafers is technologically more advanced and significantly more efficient compared to 200 mm wafers, since the bigger wafer diameter offers 2.3 times more chips per wafer.

GaN-based power semiconductors find fast adoption in industrial, automotive, and consumer, computing & communication applications, including power supplies for AI systems, solar inverters, chargers and adapters, and motor-control systems. State-of-the art GaN manufacturing processes lead to improved device performance resulting in benefits in end customers' applications as it enables efficiency performance, smaller size, lighter weight, and lower overall cost. Furthermore, 300 mm manufacturing ensures superior customer supply stability through scalability.

E&R Engineering Corp. hosted an event on August 28, 2024, in Taipei, Taiwan, where they launched the "E-Core System." This initiative, a combination of "E&R" and "Glass Core" inspired by the sound of "Ecosystem," led to the establishment of the "Glass Substrate Supplier E-Core System Alliance." The alliance aims to combine expertise to promote comprehensive solutions, providing equipment and materials for next-generation advanced packaging with glass substrates to both domestic and international customers.

E&R's E-Core Alliance includes Manz AG, Scientech for wet etching, HYAWEI OPTRONICS for AOI optical inspection, Lincotec, STK Corp., Skytech, Group Up for sputtering and ABF lamination equipment, and other key component suppliers such as HIWIN, HIWIN MIKROSYSTEM, Keyence Taiwan, Mirle Group, ACE PILLAR CHYI DING), and Coherent.

The Bluetooth Special Interest Group (SIG), the organization that oversees Bluetooth technology, announced the release of Bluetooth Channel Sounding, a new secure, fine-ranging feature that promises to enhance the convenience, safety, and security of Bluetooth connected devices. By enabling true distance awareness in billions of everyday devices, Bluetooth Channel Sounding opens countless possibilities for developers and users alike.

"Bluetooth technology has become an ingredient of everyday life," said Neville Meijers, CEO, Bluetooth Special Interest Group. "When connected devices are distance-aware, a range of new possibilities emerge. Adding true distance awareness to Bluetooth technology exemplifies the ongoing commitment of the Bluetooth SIG community to continuously enhance our connection with our devices, one another, and the world around us."

During the Semicon Taiwan 2024 summit event, TSMC VP of Advanced Packaging Technology, Jun He, spoke about the importance of merging AI chip memory and logic chips using 3D IC technology. He predicted that by 2030 the worldwide semiconductor industry would hit the $1 trillion milestone with HPC and AI leading 40 percent of the market share. In 2027, TSMC will introduce the 2.5D CoWoS technology that includes eight A16 process chipsets and 12 HBM4. AI processors that use this technology will not only be much cheaper to produce but will also provide engineers with a greater level of convenience. Engineers will have the option to write new codes into them instead. Manufacturers are cutting the SoC and HBM architectural conversion and mass production costs down to nearly one-fourth.

Nevertheless, the increasing production capacities of 3D IC technology remain the main challenge, as the size of chips and the complexity of manufacturing are decisive factors. However, the higher the size of the chips, the more chiplets are added, and thus the performance is improved, but this now makes the process even more complicated and is associated with more risks of misalignment, breakage, and extraction failure.

Epson today introduced an expansion to its SureColor V-Series UV printer line and its first UV desktop printer - the SureColor V1070. Designed to bring the power of UV printing to small businesses for an exceptional value - at less than half the cost of comparable desktop flatbed UV printers - the new A4 desktop printer is easy to use and maintain, features a compact, space-saving design and prints high quality output on a variety of materials.

"Epson is dedicated to making cutting-edge UV printing technology accessible to everyone and simplifying the process for customers starting their own business or just beginning to explore the possibilities of UV printing," said David Lopez, product manager, Professional Imaging, Epson America, Inc. "This powerful, yet affordable, desktop UV printer brings all the incredible technology of Epson's large format UV printer into a compact design that can fit into most places, allowing for high quality printing on almost anything from virtually anywhere."

Xiangdixian Computing Technology (XCT), once hailed as China's answer to NVIDIA at its peak, is now grappling with severe financial difficulties and legal challenges. The company, which has developed its own line of GPUs based on the Tianjun chips, recently admitted that its progress in "development of national GPU has not yet fully met the company's expectations and is facing certain market adjustment pressures." Despite producing two desktop and one workstation GPU model, XCT has been forced to address rumors of its closure. The company has undergone significant layoffs, but it claims to have retained key research and development staff essential for GPU advancement. Adding to XCT's woes, investors have initiated legal proceedings against the company's founder, Tang Zhimin, claiming he failed to deliver on his commitment to raising 500 million Yuan in Series B funding.

Among the complainants is the state-owned Jiangsu Zhongde Services Trade Industry Investment Fund, which has filed a lawsuit against three companies under Zhimin's control. Further complicating matters, Capitalonline Data Service is reportedly suing XCT for unpaid debts totaling 18.8 million Yuan. There are also claims that the company's bank accounts have been frozen, potentially impeding its ability to continue operations. The situation is further complicated by allegations of corruption within China's semiconductor sector, with reports of executives misappropriating investment funds. With XCT fighting for survival through restructuring efforts, its fate hangs in the balance. Without securing additional funding soon, the company may be forced to close its doors, which will blow China's GPU aspirations.

According to a recent report from Bloomberg, Intel is in talks with investment banks about a possible spin-out of its foundry business, as well as scraping some existing expansion plans to cut losses. As the report highlights, sources close to Intel noted that the company is exploring various ways to deal with the recent Q2 2024 earnings report. While Intel's revenues are in decline, they are still high. However, the profitability of running its business has declined so much that the company is now operating on a net loss, with an astonishing $1.61 billion in the red. CEO Pat Gelsinger is now exploring various ways to control these losses and make the 56-year-old giant profitable again. Goldman Sachs and Morgan Stanley are reportedly advising Intel about its future moves regarding the foundry business and overall operations.

The Intel Foundry unit represents the biggest consumer of the company's funds, as the expansion plans across the US and Europe are costing Intel billions of US Dollars. Even though the company receives various state subsidies to build semiconductor manufacturing facilities, it still has to put much of its capital to work. Given that the company is running tight on funds, some of these expansion plans that are not business-critical may get scraped. Additionally, running the foundry business is also turning out to be rather costly, with Q2 2024 recording a negative 65.5% operating margin. Separating Intel Product and Intel Foundry may be an option, or even selling the foundry business as a whole is on the table. Whatever happens next is yet to be cleared up. During the Deutsche Bank Technology Conference on Thursday, Pat Gelsinger also noted that "It's been a difficult few weeks" for Intel, with many employees getting laid off to try to establish new cost-saving measures.

Japanese professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has unveiled a revolutionary extreme ultraviolet (EUV) lithography technology that promises to significantly push down semiconductor manufacturing costs. The new technology tackles two previously insurmountable issues in EUV lithography. First, it introduces a streamlined optical projection system using only two mirrors, a dramatic simplification from the conventional six or more. Second, it employs a novel "dual line field" method to efficiently direct EUV light onto the photomask without obstructing the optical path. Prof. Shintake's design offers substantial advantages over current EUV lithography machines. It can operate with smaller EUV light sources, consuming less than one-tenth of the power required by conventional systems. This reduction in energy consumption also reduces operating expenses (OpEx), which are usually high in semiconductor manufacturing facilities.

The simplified two-mirror design also promises improved stability and maintainability. While traditional EUV systems often require over 1 megawatt of power, the OIST model can achieve comparable results with just 100 kilowatts. Despite its simplicity, the system maintains high contrast and reduces mask 3D effects, which is crucial for attaining nanometer-scale precision in semiconductor production. OIST has filed a patent application for this technology, with plans for practical implementation through demonstration experiments. The global EUV lithography market is projected to grow from $8.9 billion in 2024 to $17.4 billion by 2030, when most nodes are expected to use EUV scanners. In contrast, ASML's single EUV scanner can cost up to $380 million without OpEx, which is very high thanks to the power consumption of high-energy light UV light emitters. Regular EUV scanners also lose 40% of the UV light going to the next mirror, with only 1% of the starting light source reaching the silicon wafer. And that is while consuming over one megawatt of power. However, with the proposed low-cost EUV system, more than 10% of the energy makes it to the wafer, and the new system is expected to use less than 100 kilowatts of power while carrying a cost of less than 100 million, a third from ASML's flagship.

Micron Technology, Inc., today announced it is the first to develop PCIe Gen 6 data center SSD technology for ecosystem enablement as part of a portfolio of memory and storage products to support the broad demand for AI. Addressing these demands, Raj Narasimhan, senior vice president and general manager of Micron's Compute and Networking Business Unit, will present a keynote at FMS titled, "Data is at the heart of AI: Micron memory and storage are fueling the AI revolution," on Wednesday, Aug. 7, at 11:00 a.m. Pacific time. The session will focus on how Micron's industry-leading products are impacting AI system architectures while enabling faster and more power-efficient solutions to manage vast data sets.

At FMS, Micron will demonstrate that it is the first to develop a PCIe Gen 6 SSD for ecosystem enablement, once again showcasing its storage technology leadership. By making this technology — which delivers sequential read bandwidths of over 26 GB/s — available to partners, Micron is kickstarting the PCIe Gen 6 ecosystem. This achievement builds on Micron's recent announcement of the world's fastest data center SSD, the Micron 9550, and further bolsters Micron's leadership position in AI storage.

Lam Research Corp. today extended its leadership in 3D NAND flash memory etching with the introduction of Lam Cryo 3.0, the third generation of the company's production-proven cryogenic dielectric etch technology. As the proliferation of generative artificial intelligence (AI) continues to propel the demand for memory with higher capacity and performance, Lam Cryo 3.0 provides etch capabilities critical for the manufacturing of future leading-edge 3D NAND. Leveraging ultra cold temperatures, high power confined plasma reactor technology, and innovations in surface chemistry, Lam Cryo 3.0 etches with industry-leading precision and profile control.

"Lam Cryo 3.0 paves the way for customers on the path to 1,000-layer 3D NAND," said Sesha Varadarajan, senior vice president of Global Products Group at Lam Research. "With five million wafers already manufactured using Lam cryogenic etch, our newest technology is a breakthrough in 3D NAND production. It creates high aspect ratio (HAR) features with angstrom-level precision, while delivering lower environmental impact and more than double the etch rate of conventional dielectric processes. Lam Cryo 3.0 is the etch technology our customers need to overcome the AI era's key NAND manufacturing hurdles."

AMD today announced the signing of a definitive agreement to acquire Silo AI, the largest private AI lab in Europe, in an all-cash transaction valued at approximately $665 million. The agreement represents another significant step in the company's strategy to deliver end-to-end AI solutions based on open standards and in strong partnership with the global AI ecosystem. The Silo AI team consists of world-class AI scientists and engineers with extensive experience developing tailored AI models, platforms and solutions for leading enterprises spanning cloud, embedded and endpoint computing markets.

Silo AI CEO and co-founder Peter Sarlin will continue to lead the Silo AI team as part of the AMD Artificial Intelligence Group, reporting to AMD senior vice president Vamsi Boppana. The acquisition is expected to close in the second half of 2024.

SiliconIntervention, a design services company based in Kelowna, British Columbia, has introduced a new architecture for audio processing to enhance efficiency and reduce power consumption in wearable devices. The company's Fractal-D audio amplifier IPs is based on their New Analog design platform and uses standard CMOS processes, requiring no specialized manufacturing steps. CTO Martin Mallinson emphasizes the importance of improved efficiency and extended battery life in wearables. He notes that while standard H Bridge Class-D amplifiers achieve 80-90% efficiency at 1 W output, they typically drop to 30-40% at 10 mW. The Fractal-D architecture purportedly maintains high efficiency across both power levels, potentially extending battery life in devices like earbuds and earphones.

"Extending battery life in wearable audio products such as earbuds remains one of the most sought-after features for consumers as audio processing features continue to grow, and the Fractal-D technology is a key building block towards that goal.", commented Allan Cox, CEO of SiliconIntervention. To facilitate adoption, the company offers a customizable portfolio of features to meet specific end-product requirements besides providing product family descriptions, simulation and emulation results, and a silicon-based evaluation system. Now we have to wait and see when and what end-products will use this technology and with what effects on battery life.

PanelSemi, a developer of ultra-thin flexible LED displays and semiconductor substrates, has partnered with NGK Insulators to create high-performance hybrid packaging solutions. Leveraging its tiled thin-film transistor (TFT) circuit fabrication technology, PanelSemi is developing a hybrid circuit board that combines fine wiring and functional circuits on polyimide film with a ceramic substrate. The company is expanding into high-performance circuit boards for semiconductor modules, targeting large-scale panel manufacturing for wireless communications and opto-electronic integration. The collaboration with NGK extends the application of ceramic substrates to higher power and thermal scenarios.

NGK aims to integrate PanelSemi's circuit fabrication technology with its own products, including the ultra-compact EnerCera lithium-ion rechargeable battery, ceramic substrates, and ceramic packages. PanelSemi's HyBrid Substrate (HBS) technology platform features ultra-fine line width and spacing achieved through Thin Film (TF) and Panel Level Packaging (PLP) processes. HBS enables high-density interconnection, functioning as both an interposer and package substrate in advanced packaging, with the top die directly bonded to the HBS.

Dr. Larry Zu, Founder and CEO of Sarcina Technology, the Application Specific Advanced Packaging (ASAP) Design Service and Production leader, predicted that recent Bump Pitch Transformer (BPT) designs will speed 2.5D IC advanced packaging adoption to meet the red-hot demand for AI innovation. In remarks made in the Keysight Theater at the 61st Design Automation Conference, he envisioned new BPT technology paving the way for new artificial intelligence computing opportunities.

"We believe that the Bump Pitch Transformer architecture will accelerate the growth rate of 2.5D semiconductor packages that are key to meeting the explosive demand for AI-driven computing capabilities," Dr. Zu said during his address in the Keysight Theater.

Ansys power integrity solutions have been certified by Samsung Foundry for use with Samsung's new SF2Z 2 nm gate-all-around manufacturing technology. SF2Z includes advanced technology that moves the power distribution network to the backside of the chip — saving space, lowering costs, and improving performance. Ansys solutions enable early adopters of Samsung's technology to design leading-edge semiconductor products for HPC, smartphones, AI, data center communication, and graphics processors.

The certification includes RedHawk-SC, which provides predictively accurate signoff verification for electromigration and voltage drop (IR drop) on power distribution networks for digital designs. In addition, the Totem power integrity platform provides comprehensive evaluation for analog and mixed-signal designs. Both RedHawk-SC and Totem signoff capabilities can reduce project risk, improve reliability, and extend the longevity of chips.

FlexEnable, the leader in the development and production of flexible organic electronics for active optics and displays, today announced that the world's first mass-produced consumer product incorporating organic transistor technology has started shipping. The device, called Ledger Stax, is a secure crypto wallet developed by French company and market-leader Ledger. FlexEnable partnered with display manufacturing companies DKE (Shanghai) and Giantplus (Taiwan) to realise Ledger's design for a credit card-sized product with an E Ink display uniquely wrapped around a 180-degree bend.

Ledger Stax features a display radius of curvature never before achieved in an e-paper display product, made possible by the use of highly flexible organic thin-film transistors (OTFTs), comprising organic materials and process IP developed, supplied and licensed by FlexEnable.

Micron Technology, Inc., today announced the sampling of its next-generation GDDR7 graphics memory with the industry's highest bit density. Leveraging Micron's 1β (1-beta) DRAM technology and innovative architecture, Micron GDDR7 delivers 32 Gb/s high-performance memory in a power-optimized design. With over 1.5 TB/s of system bandwidth, which is up to 60% higher bandwidth than GDDR6, and four independent channels to optimize workloads, Micron GDDR7 memory enables faster response times, smoother gameplay and reduced processing times.

GDDR7 also provides a greater than 50% power-efficiency improvement compared to GDDR6 to better thermals and lengthen battery life, while the new sleep mode reduces standby power by up to 70%. Advanced reliability, availability and serviceability (RAS) features on Micron GDDR7 enhance device dependability and data integrity without compromising performance, broadening the spectrum of applications for Micron GDDR7 to AI, gaming and high-performance computing workloads.

Zyxel Networks' firewall solutions have been awarded Champion status in the latest Professional User Ratings (PUR) survey covering security solutions from techconsult - the renowned independent German research and analysis organisation, and part of the Heise Group.

More than 3,500 security experts from user organisations took part in techconsult's Professional User Rating: Security Solutions 2024 survey. They were asked to rate products and services in a number of areas, with vendors subsequently ranked on the basis of their Solution/Technology Excellence and Company Excellence. Zyxel Networks was one of only eight vendors to achieve the top 'Champion' status, having received the highest overall Solution/Technology Excellence rating and the fourth-highest Company Excellence ranking.

During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.

NEO Semiconductor, a leading developer of innovative technologies for 3D NAND flash and DRAM memory, today announced a performance boosting Floating Body Cell Mechanism for 3D X-DRAM. Andy Hsu, Founder & CEO presented groundbreaking Technology CAD (TCAD) simulation results for NEO's 3D X-DRAM during the 16th IEEE International Memory Workshop (IMW) 2024 in Seoul, Republic of Korea.

Neo Semiconductor reveals a unique performance boosting mechanism called Back-gate Channel-depth Modulation (BCM) for Floating Body Cell that can increase data retention by 40,000X and sensing window by 20X.

Building on the foundation of its award-winning Super X-Fi Headphone Holography, Creative Technology will be unveiling the all-new Super X-Fi Gen 4 audio profile. This latest release boasts significant enhancements in dynamic range, clarity, and spatial awareness. The Super X-Fi Gen 4 isn't just raising the bar; it's redefining the standard for immersive audio experiences. With this latest update, users can enjoy an expanded dynamic range, delivering richer, more detailed audio reproduction. Coupled with improved clarity, users can indulge in crystal-clear sound that captures every subtle nuance, while the refined sense of space offers a more expansive and lifelike soundstage.

Super X-Fi technology elevates the audio experience for users by recreating the immersive soundstage of high-end surround speaker systems within headphones, further personalized by the power of Artificial Intelligence (AI) for a remarkably natural listening experience. Since its debut at CES 2019, users and critics have been impressed by the realism of personalized audio, which is tailored according to their anthropometric profiles. From immersing in the heart-pounding action of a blockbuster movie to feeling the raw energy of a live concert or delving into the captivating world of gaming, Super X-Fi can bring it all to life with breath-taking detail and precision.

United Microelectronics Corporation ("UMC"), a leading global semiconductor foundry, today announced the industry's first 3D IC solution for RFSOI technology. Available on UMC's 55 nm RFSOI platform, the stacked silicon technology reduces die size by more than 45% without any degradation of radio frequency (RF) performance, enabling customers to efficiently integrate more RF components to address the greater bandwidth requirements of 5G.

As mobile device manufacturers pack more frequency bands in newer generations of smartphones, the company's 3D IC solution for RFSOI addresses the challenge of integrating more RF front-end modules (RF-FEM) - critical components in devices to transmit and receive data - in a device by vertically stacking dies to reduce surface area. RFSOI is the foundry process used for RF chips such as low noise amplifiers, switches, and antenna tuners. Utilizing wafer-to-wafer bonding technology, UMC's 3D IC solution for RFSOI resolves the common issue of RF interference between stacked dies. The company has received multiple patents for this process, which is now ready for production.

PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) standard, today announced the release of the CopprLink Internal and External Cable specifications. The CopprLink Cable specifications provide signaling at 32.0 and 64.0 GT/s and leverage well-established industry standard connector form factors maintained by SNIA.

"The CopprLink Cable specifications integrate PCIe cabling seamlessly with the PCIe electrical base specification, providing longer channel reach and topological flexibility," said Al Yanes, PCI-SIG President and Chairperson. "The CopprLink Cables are intended to evolve with the same connector form factors, scale for future PCIe technology generations and meet the demands of emerging applications. The Electrical Work Group has already begun pathfinding work on CopprLink Cables for PCIe 7.0 technology at 128.0 GT/s, showcasing PCI-SIG's commitment to the CopprLink Cable specifications."

Micron Technology, Inc., one of the world's largest semiconductor companies and the only U.S.-based manufacturer of memory, and the Biden-Harris Administration today announced that they have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York.

The CHIPS and Science Act grants of $6.1 billion will support Micron's plans to invest approximately $50 billion in gross capex for U.S. domestic leading-edge memory manufacturing through 2030. These grants and additional state and local incentives will support the construction of one leading-edge memory manufacturing fab to be co-located with the company's existing leading-edge R&D facility in Boise, Idaho and the construction of two leading-edge memory fabs in Clay, New York.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.