Intel Corporation today announced the appointment of Seok-Hee Lee as executive vice president of Intel Foundry, reporting directly to CEO Lip-Bu Tan. In this role, Lee will lead all advanced packaging, system integration, back-end technology development, and back-end manufacturing, strengthening Intel's ability to deliver differentiated, system-level innovation for customers.

Seok-Hee Lee Appointed to Lead Advanced Packaging
As part of the continued evolution of the Intel Foundry strategy, the company is establishing advanced packaging as a focused business with dedicated leadership. This reflects the growing importance and complexity of packaging as a key enabler of performance, power efficiency, and heterogeneous integration across AI systems.

Samsung Electronics and POSTECH have published a research paper titled "Switchable 2D-3D display through a metasurface lenticular lens" in the prestigious journal Nature, marking notable progress in next-generation display technology through industry-academia collaboration.

Rethinking 3D Displays With Metasurfaces
A metasurface lenticular lens-based switchable 2D/3D display uses an ultra-thin metalens composed of nanoscale structures to transition seamlessly between flat (2D) and stereoscopic (3D) images. A metasurface is significantly thinner while enabling complex optical functions—making it key to next-generation displays and camera systems.

Imec, a world-leading research and innovation hub in advanced semiconductor technologies, has launched a first of its kind consortium with 26 European university groups that will jointly work on the technology roadmap beyond CMOS scaling (CMOS 2.0). This initiative will focus on design automation and chip architecture research for the next generation of chips. The consortium will benefit from the NanoIC pilot line, turning academic insights into industry-focused innovations. In the future, similar consortia will be set up around advanced materials and alternative compute systems.

CMOS 2.0 refers to a new paradigm, introduced by imec, that expands the chip making toolbox beyond traditional transistor scaling and its associated scaling challenges. CMOS 2.0 allows for more design flexibility by exploiting fine-grain wafer stacking technology to improve on-chip connectivity and offer higher technology heterogeneity to the system. It will result in tailored chips comprising multiple 3D-stacked layers that fulfil smartly partitioned functions. In that way, CMOS 2.0 will provide advanced, versatile 3D stacked platforms that push the boundaries of compute performance.

ASUS has announced that, in collaboration with the National Center for High-performance Computing (NCHC) to build the new AI supercomputer, the facility is now officially in operation. It features a dual-compute architecture that includes the cluster and the latest NVIDIA GB200 NVL72 system—Taiwan's first fully liquid-cooled AI supercomputer deployment of this architecture. The Nano4 NVIDIA HGX H200 system delivers up to 81.55 PFLOPS of performance and is ranked No. 29 on the TOP500 list, marking a meaningful milestone in strengthening Taiwan's AI-computing capabilities and accelerating its intelligent transformation.

NCHC spokesperson Dr. Chia-Lee Yang said: "As the designer of the Nano4, NCHC drove the architecture, liquid-cooling strategy, and system integration. Along with AI-infrastructure expertise from ASUS, this newly built system feeds advanced computes for generative AI, big data, deep learning, and HPC, unlocking unprecedented computational capabilities for both academia and industry."

The semiconductor industry, a strategic sector vital to national security and economic development, is facing a new era of global trade policies and rising geopolitical risks. In response, the Industrial Technology Research Institute (ITRI) and SEMI co-hosted the Semicon Network Summit in Taipei on September 9. The summit was held to foster high-level global dialogue, advance AI chip collaboration, and expand talent development, with the goal of building a resilient semiconductor ecosystem.

The event drew over 600 participants from 28 countries, including the U.S., Japan, the UK, France, Germany, and the Czech Republic, highlighting the global importance of the discussions. Key figures included Taiwan's President Lai Ching-te, National Science and Technology Council Minister Cheng-Wen Wu, Minister of Economic Affairs Ming-Hsin Kung, SEMI International Board of Directors Chairman Tien Wu, ITRI President Edwin Liu, Honorary Chairman of Liberal Democratic Party's "Semiconductor Strategy Promotion Parliamentarian Alliance" Akira Amari, and TSMC Executive VP and Co-Chief Operating Officer Y.P. Chyn. Notable international officials included Czech Republic Minister for Science, Research and Innovation Marek Ženíšek, Deputy Representative of the Japan-Taiwan Exchange Association Gen Kawai, Minister Counsellor for Digital Economy Policy at the Delegation of the European Union to Japan Peter Fatelnig, and British Office Taipei Representative Ruth Bradley-Jones.

The University of Tokyo (UTokyo) and IBM have announced plans to deploy the latest 156-qubit IBM Heron quantum processing unit (QPU), which will be operational in the IBM Quantum System One administered by UTokyo for the members of the Quantum Innovation Initiative (QII) Consortium. The IBM Heron QPU, which features a tunable-coupler architecture, delivers a significantly higher performance than the processor previously installed in 2023.

This is the second update of the IBM Quantum System One as part of the collaboration between UTokyo and IBM. It was first deployed with a 27-qubit IBM Falcon QPU, before being updated to a 127-qubit IBM Eagle QPU in 2023. It is now transitioning to the latest generation highly performant IBM Heron later this year. IBM has deployed four Heron-based systems worldwide and their performance shows significant improvement over the previous Eagle QPU, with a 3-4x improvement in two-qubit error rates; an order of magnitude improvement in device-wide performance benchmarked by errors across 100-qubit long layers; continued improvement in speed, with a 60 percent increase in CLOPS expected; and a system uptime of more than 95%. The latest IBM Heron processor has continued to demonstrate immense value in orchestrating utility-level workloads, to date, with multiple published studies leveraging these systems' capability of achieving more than 5,000 gate operations.