Introduction

AMD today unveiled its 6th Gen EPYC 9006 "Venice" and EPYC "Verano" server processors in the SP7 package. The two are powered by the company's latest Zen 6 microarchitecture that aims to significantly increase CPU core counts and IPC over the current "Zen 5," besides introducing a major upgrade to the platform I/O. Today, the company is only announcing its EPYC server processors, client Ryzen processors powered by Zen 6 are expected later.

To begin with, Zen 6 introduces the first major increase in core-count for the performance chiplet since "Zen 2" from eight years ago. Built on the 2 nm TSMC N2 foundry node, the CCD features 12 Zen 6 performance cores in a single CPU core complex (CCX), sharing 48 MB of L3 cache. This represents a 50% increase in core- and last-level cache counts.

The real story of the day, however, is the compact Zen 6c core. AMD claims to have given their compact core its biggest generational IPC and core-count uplift. AMD's C-cores are spiritually E-cores, but are physically compacted P-cores that feature the same core components and core-level caches, but with limited clock-speed headroom compared to the regular cores. With "Zen 6c," AMD claims to have increased the IPC, maximum clock-speed, and core-count for the Zen 6c chiplet, significantly over the previous-generation "Zen 5c" chiplet.



AMD is introducing a new pure Zen 6c CCD, built on the same 2 nm TSMC N2 foundry node as the Zen 6 chiplet, which increases the per-CCD core-count to a whopping 32 cores. That's not all, AMD also quadrupled the on-die L3 cache for this CCD to a generous 128 MB. So, not only is the cache doubled, but also, the L3 cache per-core has doubled from 2 MB/core to 4 MB. Since Zen 6 retains SMT like all previous generations of "Zen," this CCD is 32-core/64-thread, allowing AMD to build its latest EPYC Verano processors with a maximum of 256-cores/512-threads by using eight CCDs.

AMD is claiming a massive 20% IPC uplift for Zen 6 over "Zen 5" in enterprise and cloud server workloads; and a 31% IPC uplift in AI workloads. It is very important to note here that AMD is only testing EPYC-relevant benchmarks to arrive at these numbers, and the IPC increase for future Ryzen client processors powered by Zen 6 cores could be significantly different as those are assessed on a very different set of benchmarks, with a very different platform. It's also important to note here that Zen 6 and Zen 6c, like all previous versions of regular and compacted cores of "Zen," provide an identical IPC to each other, and the only thing separating them is clock speed limitations on the compacted core, since cache amount has been increased this generation.

The headline numbers are easy to repeat and hard to believe. A single Venice socket holds up to 256 cores. It feeds them from 16 channels of DDR5 memory, which at MRDIMM speeds works out to 1.6 TB/s of memory bandwidth per socket. It is the first x86 processor with PCIe Gen 6, and the first server CPU of any kind to support JEDEC-standard MRDIMM. AMD claims 2.0x the SPECint 2026 throughput of 5th Gen "Turin," and 2.4x the floating-point throughput.

AMD is planning its next generation Ryzen desktop processors on the same Zen 6 chiplet you'll see throughout this article, however, today's launch is purely centered on EPYC—the company did not measure performance in any consumer/client applications, and even its IPC calculations for Zen 6 are purely theoretical.

Venice SP7 platforms are shipping now. Microsoft Azure announced a preview of its HDv2 instances built on Venice, making it the first cloud to offer 6th Gen EPYC. The rest of the family arrives through 2027.

Four Products, One Generation

AMD is not shipping just one Venice chip. It is shipping four distinct products under the EPYC 9006 banner, each with its own socket, memory type and target workload. This is a bigger spread than any previous EPYC generation, and it reflects AMD's view that the data center has fragmented into workloads that want very different things from a CPU.

Venice 9006 SP7
The flagship. Up to 256 Zen 6c cores or 96 Zen 6 cores, 16 channels of DDR5, 96 lanes of PCIe Gen 6 in single-socket configurations, and both 1P and 2P support. AMD positions it for cloud, HPC, AI host nodes and agentic services. This is the part shipping today.

Venice 9006 SP8
A smaller socket for mainstream servers. Up to 128 Zen 6c cores or 96 Zen 6 cores, 8 memory channels with two DIMMs per channel, and more PCIe lanes than SP7 at 128 per socket. Aimed at enterprise, storage, edge and telco. Available in the first half of 2027.

Venice-X 9006X SP7
The 3D V-Cache part. Up to 96 cores with 1152 MB of total L3 cache, in the same SP7 socket. AMD calls it "the best 3D V-Cache yet," and it is the first X-series part since Genoa-X—there was no Turin-X. Targeted at EDA and technical computing. Available in the second half of 2027.

Verano 9006 LP
The odd one out, and the most interesting. Verano drops DDR5 entirely in favor of 24 channels of LPDDR5X on field-replaceable SOCAMM modules. It is built for AI host nodes, where the CPU's job is to feed GPUs rather than do the work itself. Also second half of 2027.

Venice-X vs its Predecessors

The L3 cache total is unchanged from Genoa-X, but everything around it moved. Clock speed is up by 1.60 GHz, memory bandwidth is up 3.6x, and the cache is now spread over fewer but larger cache slices. AMD describes it as 3x the cache per core compared to a standard 96-core Venice, which carries 384 MB across its eight Zen 6 CCDs.

The Full Stack

AMD did not present a server SKU table at the event, but its product pages for the 9006 series are live, and our CPU database has them: 31 models across the two sockets, with launch prices. Everything on this page comes from our CPU database rather than from AMD's briefings. It's possible that the final products end up significantly different from what you see here.

SP7

SP8