AMD EPYC Architecture & Technical Overview 29

AMD EPYC Architecture & Technical Overview

"Zen" Microarchitecture »

Introduction


AMD put nearly all their eggs in the Zen architecture bucket after having given up years of market share to Intel in the consumer, HEDT, and even server industry market segments. To many, this was a massive risk considering the ~40% IPC increase promised (and required to compete), but with the Ryzen desktop processors, AMD showed that they did achieve that and more. Ryzen CPUs introduced up to 8 cores and16 threads to customers previously getting half that number from Intel and carved out a place in the market thanks to their price/performance ratio, especially with applications that take advantage of parallel workload processing.

With their upcoming Threadripper series, AMD is making use of their new Infinity Fabric design to essentially put the equivalent of up to two 8-core CPUs into one massive package. Featuring up to 16 cores and 32 threads due to their Simultaneous Multithreading (SMT), AMD will challenge Intel for the HEDT platform for the prosumer and professional alike. While that is upcoming still, AMD today took the wraps off their solution for the datacenter and server market.

The words "EPYC" and "32C/64T" were in high flow in the PC tech press media coverage since before Computex even, and with the launch today, we get detailed information on the EPYC platform and all optimizations AMD has done.


This article aims to bring forth the salient features of the EPYC server architecture. We will go over the lineup, take a closer look at the new "Zen" core design, understand better how the memory and IO connectivity work, and describe the new security features. As such, we thank AMD for providing said information. Let us begin with a look at the entire EPYC CPU lineup now.

The Lineup


AMD has announced a plethora of both 2P and 1P socket CPUs under the EPYC brand today, with the 2P system CPUs beginning with the EPYC 7251 8C/16T 120 W TDP CPU and culminating in the powerhouse EPYC 7601 32C/64T 180 W TDP CPU. There are thus a total of nine 2P offerings with core counts ranging from 8 to 32, and all of them offer 128 PCIe Gen 3.0 lanes with support for 8-channels of DDR4 2667 MHz system memory (up to 2 TB per CPU). Note the varying TDP for some of the SKUs - this is a result of the increased control over the performance/power balance across the entire system.

The 1P system CPUs are arguably even more interesting, albeit fewer in number. We get the same 8-channel DDR4 memory and 128 PCIe lane support here, meaning there is 2P feature set support with the 1P systems as well. The three offerings have core counts ranging from 16 to 32 with the top-end SKU having a slightly smaller boost clock compared to the 2P flagship.


We now have pricing and retail availability information for most of the SKUs, and it has been tabulated above. AMD is hitting Intel's respective competition at a lower price point here.
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