Tuesday, April 2nd 2013
GLOBALFOUNDRIES Demonstrates 3D TSV Capabilities on 20nm Technology
GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GLOBALFOUNDRIES' leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today's electronic devices.
TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers.
GLOBALFOUNDRIES utilizes a "via-middle" approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, GLOBALFOUNDRIES engineers have developed a proprietary contact protection scheme. This scheme enabled the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.
"Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality," said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. "Our next step is to leverage Fab 8's advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain."
As the fabless-foundry business model evolves to address the realities of today's dynamic market, foundries are taking on increasing responsibility for managing the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs. To help address these challenges, GLOBALFOUNDRIES is engaging early with partners to jointly develop solutions that will enable the next wave of innovation in the industry. This open and collaborative approach will give customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.
TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers.
GLOBALFOUNDRIES utilizes a "via-middle" approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, GLOBALFOUNDRIES engineers have developed a proprietary contact protection scheme. This scheme enabled the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.
"Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality," said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. "Our next step is to leverage Fab 8's advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain."
As the fabless-foundry business model evolves to address the realities of today's dynamic market, foundries are taking on increasing responsibility for managing the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs. To help address these challenges, GLOBALFOUNDRIES is engaging early with partners to jointly develop solutions that will enable the next wave of innovation in the industry. This open and collaborative approach will give customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.
20 Comments on GLOBALFOUNDRIES Demonstrates 3D TSV Capabilities on 20nm Technology
AMD, die shrink Yer CPUs, please! :D
AMD was pushing the 32nm process to the limit for quite some time now. They were doing miracles with it power-efficiency-wise, but now there is simply no room where to improve it on the 32nm. Going 20nm would really help them in that regard.
This is especially good news for AMD if they can apply this tech across their various tech product lines ( GPUs, APUs, CPUs, memory chips, etc). Certainly, Intel has the upper hand in offering smaller and smaller nodes faster than anyone else, but TSV gives AMD and other GF partners the ability to stretch out the comeptitive lifetime for using a particular node, especially as it becomes more and more difficult (and expensive) to produce ever smaller transistors. TSV sounds like it'll be really beneficial for AMD's future GPU since waiting for new nodes to become available and mature to acceptable production yields, is a major factor in why AMD and Nvidia have had to delay products over recent years. Now they can simply (or at least more simply than transitioning to a new node) add an additional layer to an existing GPU design to theoretially double performance. Of couse, I am no engineer and I may be over simplifying everything. There may be issues and limitations to TSV like higher heat production and voltage leakage or limits on how many layers are doable for a particular node type. Obviously, AMD won't be able to appy this technology to their products at least for a few more years, but hopefully it will come sooner rather than later, and give AMD the ability to update products more frequently and stay on schedule when releasing new parts.
But putting jokes aside, this is great news indeed. We need much more competition on the CPU side, I hope AMD can make Intel sweat a little bit soon, and force them to make even better CPUs and drop prices:toast:
I see multi-layer chips as being useful for eDRAM, which can be put on the lower layer(s) with the main processor on the top most layer. This is similar to Intel's Haswell and NVidia's Volta, except they use memory on the same package whereas this would be in the die stack and could potentially have a much much wider bus.
the only thing intel have been doing is improve the cache subsystem with more entries and queues here and there, and improved prefetcher and branch predictors, but that will only go so far on this same old design, eventually they will need to make a radical redesign to the whole core to make room for improvement. bulldozer wasnt ideal, but surely it opened much more room for improvement, and i see the whole module idea going a long way even much longer after excavatorthis^
nvidia already stated they will use stacked dram for their gpus in their future roadmap but its pretty much only to add capacity per chip(if i remember correctly i dont remember them saying it will be part of the same die did they?), which is expected in the next few years. but for gpus and cpus idk how likely this could work other than maybe having the l3 cache at the lower level and the cores on top, would make an interesting twist.
on another I hope this makes ssds cheaper tho thats for sure!
They completely redesigned the out-of-order execution (from scratch) in Sandy Bridge and the new one turned out to be pretty awesome tbh, it's one of the main reason it's ended up being one of the best CPUs ever of it's time (if not the one).
They not only "improved" the cache but also added a new very high speed ring bus and other things like QuickSync or 6GBPs SATA to the chipset as well.
Hell, it was beating the 980X Extreme in many of the tests, if this is the result when they don't introduce "radical changes", I have to admit I'm quite OK if they just go like that every time.