Wednesday, November 12th 2014
TSMC 16FinFET Plus Process Achieves Risk Production Milestone
TSMC today announced its 16-nanometer FinFET Plus (16FF+) process is now in risk production. This enhanced version of TSMC's 16FF process operates 40% faster than the company's planar 20-nanometer system-on-chip (20SoC) process, or consumes 50% less power at the same speed. It offers customers a new level of performance and power optimization targeted at the next generation of high-end mobile, computing, networking, and consumer applications.
TSMC's 16nm process offers an extended scaling of advanced SoC designs and is verified to reach speeds of 2.3GHz with ARM's "big" Cortex-A57 in high-speed applications while consuming as little as 75mW with the "LITTLE" Cortex-A53 in low-power applications. It is making excellent progress in yield learning, and has achieved the best technology maturity at the same corresponding stage as compared to all TSMC's previous nodes.
"Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology to achieve maximum value for customers' products," said TSMC President and Co-CEO, Dr. Mark Liu. "We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals."
TSMC's comprehensive 16FF+ design ecosystem supports a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated. Backed by the resources of the biggest design ecosystem in the industry, TSMC and its customers are starting intensive design engagements, paving the way for future product tape-outs, pilot activities and early sampling.
The 16FF+ process is on track to pass full reliability qualification later in November, and nearly 60 customer designs are currently scheduled to tape out by the end of 2015. Due to rapid progress in yield and performance, TSMC anticipates 16FF+ volume ramp will begin around July in 2015.
"TSMC 16FF+ process technology enables Avago to design highly optimized custom silicon solutions for networking applications in cloud datacenters and enterprise networks," said Hock Tan, President and CEO of Avago Technologies Limited. "TSMC's 16FF+ process technology in combination with Avago's industry leading SerDes, memory, processor cores, and design implementation techniques deliver unparalleled time-to-market, performance and power benefits to OEM customers."
"Sixteen-nanometer FinFET Plus technology provides compelling performance per watt advantages, enabling a myriad wave of market inflection points such as Internet of Things, 5G networks and software defined networks," said Tom Deitrich, Senior Vice President and General Manager for Freescale's Digital Networking group. "Powering the new virtualized network, a new family of Layerscape multicore processors using ARM and Power Architecture technologies will be Freescale's first offerings to leverage this innovative process technology."
"Our collaboration with TSMC on 16FF+ technology will give LG strong competitiveness with respect to power, performance and area in the mobile AP market," said Bo-ik Sohn, Senior Vice President at LG Electronics. "We believe that the product made through our partnership with TSMC will meet the widespread consumer demand for distinctive mobile technology."
"TSMC is a trusted technology partner, helping to drive MediaTek's success over the past decade to deliver market leading SoCs," said CJ Hsieh, President of MediaTek. "With TSMC's first ever FinFET 3D architecture and enhanced plus version, MediaTek advances mobile and home entertainment SoCs demonstrating even faster speed, optimized power and reduced chip size. The performance boosts and power reduction for MediaTek's processors and modem technologies, compared to previous generations, has proven TSMC's 16FF+ to be a highly competitive process technology for our chipsets."
"NVIDIA and TSMC have collaborated for more than 15 years to deliver complex GPU architectures on state-of-the-art process nodes," said Jeff Fisher, Senior Vice President, GeForce Business Unit, NVIDIA. "Our partnership has delivered well over a billion GPUs that are deployed in everything from automobiles to supercomputers. Through working together on the next-generation 16nm FinFET process, we look forward to delivering industry-leading performance and power efficiency with future GPUs and SOCs."
"Our partnership with TSMC enables us to address evolving semiconductor technologies and to provide state-of-the-art solutions for our customers in the automotive, industrial and ICT fields," said Hisao Sakuta, Chairman & CEO of Renesas Electronics Corporation. "Now, we want to take full advantage of the 16FF+ technology to deliver added values for our customers in the advanced automotive information and ICT markets."
"TSMC is once again demonstrating their leadership in the industry by delivering their 16FF+ process with exceptional results," said Moshe Gavrielov, President and CEO of Xilinx. "This risk production milestone achievement and our continued close collaboration is enabling Xilinx to realize the industry's highest FPGA performance per watt and an unprecedented level of programmable systems integration with the industry's first All Programmable MPSoC and 3rd Generation 3D ICs."
TSMC's 16nm process offers an extended scaling of advanced SoC designs and is verified to reach speeds of 2.3GHz with ARM's "big" Cortex-A57 in high-speed applications while consuming as little as 75mW with the "LITTLE" Cortex-A53 in low-power applications. It is making excellent progress in yield learning, and has achieved the best technology maturity at the same corresponding stage as compared to all TSMC's previous nodes.
"Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology to achieve maximum value for customers' products," said TSMC President and Co-CEO, Dr. Mark Liu. "We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals."
TSMC's comprehensive 16FF+ design ecosystem supports a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated. Backed by the resources of the biggest design ecosystem in the industry, TSMC and its customers are starting intensive design engagements, paving the way for future product tape-outs, pilot activities and early sampling.
The 16FF+ process is on track to pass full reliability qualification later in November, and nearly 60 customer designs are currently scheduled to tape out by the end of 2015. Due to rapid progress in yield and performance, TSMC anticipates 16FF+ volume ramp will begin around July in 2015.
"TSMC 16FF+ process technology enables Avago to design highly optimized custom silicon solutions for networking applications in cloud datacenters and enterprise networks," said Hock Tan, President and CEO of Avago Technologies Limited. "TSMC's 16FF+ process technology in combination with Avago's industry leading SerDes, memory, processor cores, and design implementation techniques deliver unparalleled time-to-market, performance and power benefits to OEM customers."
"Sixteen-nanometer FinFET Plus technology provides compelling performance per watt advantages, enabling a myriad wave of market inflection points such as Internet of Things, 5G networks and software defined networks," said Tom Deitrich, Senior Vice President and General Manager for Freescale's Digital Networking group. "Powering the new virtualized network, a new family of Layerscape multicore processors using ARM and Power Architecture technologies will be Freescale's first offerings to leverage this innovative process technology."
"Our collaboration with TSMC on 16FF+ technology will give LG strong competitiveness with respect to power, performance and area in the mobile AP market," said Bo-ik Sohn, Senior Vice President at LG Electronics. "We believe that the product made through our partnership with TSMC will meet the widespread consumer demand for distinctive mobile technology."
"TSMC is a trusted technology partner, helping to drive MediaTek's success over the past decade to deliver market leading SoCs," said CJ Hsieh, President of MediaTek. "With TSMC's first ever FinFET 3D architecture and enhanced plus version, MediaTek advances mobile and home entertainment SoCs demonstrating even faster speed, optimized power and reduced chip size. The performance boosts and power reduction for MediaTek's processors and modem technologies, compared to previous generations, has proven TSMC's 16FF+ to be a highly competitive process technology for our chipsets."
"NVIDIA and TSMC have collaborated for more than 15 years to deliver complex GPU architectures on state-of-the-art process nodes," said Jeff Fisher, Senior Vice President, GeForce Business Unit, NVIDIA. "Our partnership has delivered well over a billion GPUs that are deployed in everything from automobiles to supercomputers. Through working together on the next-generation 16nm FinFET process, we look forward to delivering industry-leading performance and power efficiency with future GPUs and SOCs."
"Our partnership with TSMC enables us to address evolving semiconductor technologies and to provide state-of-the-art solutions for our customers in the automotive, industrial and ICT fields," said Hisao Sakuta, Chairman & CEO of Renesas Electronics Corporation. "Now, we want to take full advantage of the 16FF+ technology to deliver added values for our customers in the advanced automotive information and ICT markets."
"TSMC is once again demonstrating their leadership in the industry by delivering their 16FF+ process with exceptional results," said Moshe Gavrielov, President and CEO of Xilinx. "This risk production milestone achievement and our continued close collaboration is enabling Xilinx to realize the industry's highest FPGA performance per watt and an unprecedented level of programmable systems integration with the industry's first All Programmable MPSoC and 3rd Generation 3D ICs."
12 Comments on TSMC 16FinFET Plus Process Achieves Risk Production Milestone
Die space costs money, shrinking the dies going into all the consoles will give them a higher return, also it should improve the per watt performance of the CPU and GPUs which are all looking very long in the tooth.
From that second article I find it interesting that Hynix is so strong at 6th place.
I'm pretty sure that at least some of AMD's 300 series will still be on 28nm. 16nm is too far away realistically, and 20nm has already demonstrated that it isn't cut out for high power IC's. Given that the scuttlebutt is that at least one (Fiji) might sport HBM it seems a contradiction in terms to suggest it will be 20nm given IMC's demand a good power budget...and Fiji is supposedly sporting a very wide memory interface by GPU standards. I'd also note that HBM is limited to 4GB (4 x 1GB stacks) in it's first iteration - wide interface and high bandwidth but a pretty lousy framebuffer/marketing point, so it might be possible that Fiji has a tiered memory fit-out (HBM + GDDR5) assuming the latency differential can be addressed - which would argue even more against 20nm.