AMD Capilano

Capilano

Block Diagram

AMD's Capilano GPU uses the TeraScale 2 architecture and is made using a 40 nm production process at TSMC. With a die size of 104 mm² and a transistor count of 627 million it is a small chip. Capilano supports DirectX 11.2 (Feature Level 11_0). For GPU compute applications, OpenCL version 1.2 can be used. It features 400 shading units, 20 texture mapping units and 8 ROPs.

Further reading: Evergreen Series Instruction Set Architecture

Graphics Processor

Released: Oct 28th, 2009

GPU Name: Capilano

Desktop Variant: Redwood

Generation: Evergreen

Architecture: TeraScale 2

Foundry: TSMC

Process Size: 40 nm

Transistors: 627 million

Density: 6.0M / mm²

Die Size: 104 mm²

Package: FCBGA-962

Graphics Features

DirectX: 11.2 (11_0)

OpenGL: 4.4

OpenCL: 1.2

Vulkan: N/A

Shader Model: 5.0

WDDM: 1.3

Compute: GFX4

DCE: 4.0

UVD: 2.3

Render Config

Shading Units: 400

TMUs: 20

ROPs: 8

Compute Units: 5

Z-Stencil: 40

L1 Cache: 8 KB per CU

L2 Cache: 256 KB

Max. TDP: 30 W

All TeraScale 2 GPUs

AMD GPU Architecture History

2023 CDNA 3.0
2022-2024 RDNA 3.0
2021 CDNA 2.0
2020 CDNA 1.0
2020-2023 RDNA 2.0
2019-2020 RDNA 1.0
2018-2022 GCN 5.1
2017-2020 GCN 5.0
2016-2020 GCN 4.0
2014-2019 GCN 3.0
2013-2017 GCN 2.0
2011-2020 GCN 1.0
2010-2013 TeraScale 3
2009-2015 TeraScale 2
2005-2013 TeraScale
2005-2007 Ultra-Threaded SE

Graphics cards using the AMD Capilano GPU

Name	Chip	Memory	Shaders	TMUs	ROPs	GPU Clock	Memory Clock
AMD Radeon HD 6550M	Capilano PRO	1024 MB	400	20	8	600 MHz	900 MHz
AMD Radeon HD 6530M	Capilano LP	1024 MB	400	20	8	450 MHz	900 MHz
AMD Radeon HD 6570M	Capilano XT	1024 MB	400	20	8	650 MHz	800 MHz
AMD Radeon HD 6570M Mac Edition	Capilano XT	1024 MB	400	20	8	600 MHz	800 MHz