Intel is preparing to unveil its cutting-edge Xeon 6 series server CPUs, known as Granite Rapids and Sierra Forest. These forthcoming processors are set to deliver a significant boost in performance, foreshadowing a new era of computing power, albeit with a trade-off in increased power consumption. Two days ago, Yuuki_Ans posted information about the Beechnut City validation platform. Today, he updated the X thread with more information that Intel is significantly boosting core counts across its new Xeon 6 lineup. The flagship Xeon 6 6980P is a behemoth, packing 128 cores with a blistering 500 Watt Thermal Design Power (TDP) rating. In fact, Intel is equipping five of its Xeon 6 CPUs with a sky-high 500 W TDP, including the top four Granite Rapids parts and even the flagship Sierra Forest SKU, which is composed entirely of efficiency cores. This marks a substantial increase from Intel's previous Xeon Scalable processors, which maxed out at 350-385 Watts.

The trade-off for this performance boost is a dramatic rise in power consumption. By nearly doubling the TDP ceiling, Intel can double the core count from 64 to 128 cores on its Granite Rapids CPUs, vastly improving its multi-core capabilities. However, this focus on raw performance over power efficiency means server manufacturers must redesign their cooling solutions to accommodate Intel's flagship 500 W parts adequately. Failure to do so could lead to potential thermal throttling issues. Intel's next-gen Xeon CPU architectures are shaping up to be one of the most considerable generational leaps in recent memory. Still, they come with a trade-off in power consumption that vendors and data centers will need to address. Densely packing thousands of these 500-Watt SKUs will lead to new power and thermal challenges, and we wait to see future data center projects utilizing them.

Intel's next-generation Xeon 6 processors, codenamed Granite Rapids and Sierra Forest, are poised to shake up the CPU market with its cutting-edge architecture and features. Hardware leaker YuuKi_AnS has provided the first glimpse of Intel's upcoming platform, revealing images of the vibrant red-colored validation platform dubbed Beechnut City. Beechnut City serves as a crucial testing ground for the forthcoming Xeon 6 series, which will comprise both the Granite Rapids (P-Core architecture) and Sierra Forest (E-Core architecture) processors. Although not intended for commercial release, this validation platform is designed to rigorously test and validate the new CPUs. The dual-socket LGA-4710 platform boasts the capability to support up to two Sierra Forest or Granite Rapids CPUs simultaneously, promising a significant performance boost for data centers and other high-performance computing applications.

According to YuuKi_AnS's leaks, the Xeon 6 series may feature SKU names such as Xeon 6 6900E/P (Platinum), Xeon 6 6700E/P (Gold), Xeon 6 6500P (Silver), and Xeon 6 6300P (Bronze). One of the platform's standout features is its support for 32 DIMMs in 16-channel memory system, similar to the previously discussed Avenue City platform, which can accommodate up to 24 DDR5-6400 DIMMs in 12-channel memory. The Sierra Forest variant with 144 cores is expected to launch in the first half of this year, while the 288-core variant is slated for release in the second half. Notably, the Xeon 6 series will mark a significant shift in Intel's CPU lineup, as it will be the first CPU series to feature only Efficient cores, akin to AMD's Zen Dense cores (such as Bergamo). This move aligns with Intel's strategy to cater to the growing demand for high-performance computing and data center applications, where energy efficiency and performance are essential.There is also a picture of server configuration of Avenue City was pictured a while ago, thanks to the previous leak of Yuuki_Ans, which can be seen below in addition to Beechnut City platform.

During the Vision 2024 event, Intel announced that its upcoming Xeon processors will be branded under the new "Xeon 6" moniker. This rebranding effort aims to simplify the company's product stack and align with the recent changes made to its consumer CPU naming scheme. In contrast to the previous "x Generation Xeon Scalable", the new branding aims to simplify the product family. The highly anticipated Sierra Forest and Granite Ridge chips will be the first processors to bear the Xeon 6 branding, and they are set to launch in the coming months. Intel has confirmed that Sierra Forest, designed entirely with efficiency cores (E-cores), remains on track for release this quarter. Supermicro has already announced early availability and remote testing programs for these chips. Intel's Sierra Forest is set to deliver a substantial leap in performance. According to the company, it will offer a 2.4X improvement in performance per watt and a staggering 2.7X better performance per rack compared to the previous generation. This means that 72 Sierra Forest server racks will provide the same performance as 200 racks equipped with older second-gen Xeon CPUs, leading to significant power savings and a boost in overall efficiency for data centers upgrading their system.

Intel has also teased an exciting feature in its forthcoming Granite Ridge processors-support for the MXFP4 data format. This new precision format, backed by the Open Compute Project (OCP) and major industry players like NVIDIA, AMD, and Arm, promises to revolutionize performance. It could reduce next-token latency by up to 6.5X compared to fourth-gen Xeons using FP16. Additionally, Intel stated that Granite Ridge will be capable of running 70 billion parameter Llama-2 models, a capability that could open up new possibilities in data processing. Intel claims that 70 billion 4-bit models run entirely on Xeon in just 86 milliseconds. While Sierra Forest is slated for this quarter, Intel has not provided a specific launch timeline for Granite Ridge, stating only that it will arrive "soon after" its E-core counterpart. The Xeon 6 branding aims to simplify the product stack and clarify customer performance tiers as the company gears up for these major releases.

A CPU-Z screenshot has been shared by YuuKi_AnS—the image contains details about an alleged next-gen Intel Xeon Scalable processor engineering sample (ES). The hardware tipster noted in (yesterday's post) that an error had occurred in the application's identification of this chunk of prototype silicon. CPU-Z v2.09 has recognized the basics—an Intel Granite Rapids-SP processor that is specced with 80 cores, 2.5 GHz max frequency, a whopping 672 MB of L3 cache, and a max. TDP rating of 350 W. The counting of 320 threads seems to be CPU-Z's big mistake here—previous Granite Rapids-related leaks have not revealed Team Blue's Hyper-Threading technology producing such impressive numbers.

The alleged prototype status of this Xeon chip is very apparent in CPU-Z's tracking of single and multi-core performance—the benchmark results are really off the mark, when compared to finalized current-gen scores (produced by rival silicon). Team Blue's next-gen Xeon series is likely positioned to catch up with AMD EPYC's deployment of large core counts—"Granite Rapids" has been linked to the Intel 3 foundry node, reports from last month suggest that XCC-type processors could be configured with "counts going up to 56-core/112-threads." Micron is prepping next-gen "Tall Form Factor" memory modules, designed with future enterprise processor platforms in mind—including Intel's Xeon Scalable "Granite Rapids" family. Industry watchdogs posit that Team Blue will be launching this series in the coming months.

Micron representatives showcased new products at last week's NVIDIA GTC event—one eye-catching DIMM is all set for deployment within next-generation servers. Tom's Hardware spent some time at Micron's booth—they found out that the "Tall Form Factor" 256 GB DDR5-8800 Multiplexer Combined Ranks (MCR) DIMM is being prepared for future enterprise processor platforms, including Intel's Xeon Scalable "Granite Rapids" family. A lone "tall" prototype module was exhibited, but company representatives indicated that standard height MCRDIMMs are in development. Tom's Hardware found out that these will compact enough to fit in 1U-sized server systems. According to their in-person experience: "(Micron's) 256 GB MCRDIMMs are based on monolithic 32 Gb DDR5 ICs, but the tall one places 80 DRAM chips on both sides of the module, whereas the standard one uses 2Hi stacked packages, which means that they run slightly hotter due to less space for thermal dissipation. In any case, the tall module consumes around 20 W, which isn't bad as Micron's 128 GB DDR5-8000 RDIMM consumes 10 W at DDR5-4800."

In a recent earnings call, Micron CEO Sanjay Mehrotra, commented on his company's latest technology: "we (have) started sampling our 256 GB MCRDIMM module, which further enhances performance and increases DRAM content per server." Next-gen Intel Xeon platforms are expected to support 12 or 24 memory slots per processor socket. Enabled datacenter machines could be specced with total 3 TB or 6 TB (DDR5-8000) memory capacities. AnandTech has summarized the benefits of Micron's new part: "Multiplexer Combined Ranks (MCR) DIMMs are dual-rank memory modules featuring a specialized buffer that allows both ranks to operate simultaneously. This buffer enables the two physical ranks to operate as though they were separate modules working in parallel, which allows for concurrent retrieval of 128 bytes of data from both ranks per clock cycle—compared to 64 bytes per cycle when it comes to regular memory modules—effectively doubling performance of a single module." The added complexity is offset by significant performance boons—ideal for advanced server-side AI-crunching in the future.

At MWC 2024, Intel announced new platforms, solutions and services spanning network and edge AI, Intel Core Ultra processors and the AI PC, and more. In an era where technological advancements are integral to staying competitive, Intel is delivering products and solutions for its customers, partners and expansive ecosystem to capitalize on the emerging opportunities of artificial intelligence and built-in automation, to improve total cost of ownership (TCO) and operational efficiency, and to deliver new innovations and services.

Across today's announcements, Intel is focused on empowering the industry to further modernize and monetize 5G, edge and enterprise infrastructures and investments, and to take advantage of bringing AI Everywhere. For more than a decade, and alongside Intel's customers and partners, the company has been transforming today's network infrastructure from fixed-function to a software-defined platform and driving success at the edge with more than 90,000 real-world deployments.

Feast your eyes on the first pictures of an Intel "Granite Rapids" Xeon processor wafer, courtesy of Andreas Schilling with HardwareLuxx.de. This is Intel's first commercial silicon built on the new Intel 3 foundry node, which is expected to be the company's final silicon fabrication node to implement FinFET technology; before the company switches to Nanosheets with the next-generation Intel 20A. Intel 3 offers transistor densities and performance competitive to TSMC N3 series, and Samsung 3GA series nodes.

The wafer contains square 30-core tiles, two of which make up a "Granite Rapids-XCC" processor, with CPU core counts going up to 56-core/112-threads (two cores left unused per tile for harvesting). Each of the 30 cores on the tile is a "Redwood Cove" P-core. In comparison, the current "Emerald Rapids" Xeon processor uses "Raptor Cove" cores, and is built on the Intel 7 foundry node. Intel is planning to overcome the CPU core-count deficit to AMD EPYC, including the upcoming EPYC "Turin" Zen 5 processors with their rumored 128-core/256-thread counts, by implementing several on-silicon fixed-function accelerators that speed up popular kinds of server workloads. The "Redwood Cove" core is expected to be Intel's first IA core to implement AVX10 and APX.

Intel has begun rolling out software binaries compiled with support for upcoming Advanced Performance Extensions (APX) and Advanced Vector Extensions 10 (AVX10) instruction set extensions in their Clear Linux distribution, ahead of any processors officially supporting these capabilities launching. Clear Linux is focusing first on optimized APX and AVX10 versions of foundational software libraries like glibc and Python. This builds on Clear Linux's existing support for optimized x86-64-v2, v3, and v4 code paths, leveraging the latest microarchitectural features of each Intel CPU generation. The rationale is to prepare Clear Linux to fully leverage the performance potential of next-generation Intel Xeon server processors, code-named Granite Rapids, expected to launch later this year.

Granite Rapids will introduce AVX10.1/512 instructions as well as the new APX capabilities, which are currently not well documented implementation wise. By rolling out APX/AVX10 support in software now, Clear Linux aims to have an optimized ecosystem ready when the new processors officially ship. Initially, APX and AVX10 support is being added using the existing GCC compiler. Still, Clear Linux notes they will transition to using the upcoming GCC 14 release with more mature support for these instruction sets. The goal is to eventually have many Clear Linux packages compiled with APX/AVX10 code paths to maximize performance on future Intel CPUs. This continues Clear Linux's strategy of leveraging Intel's latest hardware capabilities in software.

Intel has recently updated its Software Development Emulator (now version 9.33.0)—InstLatX64 noted some intriguing cache designations for Fifth Generation Xeon Scalable Processors. The "Emerald Rapids" family was introduced at last December's "AI Everywhere" event—with sample units released soon after for review. Tom's Hardware was impressed by the Platinum 8592+ CPU's tripled L3 Cache (over the previous generation): "(it) contributed significantly to gains in Artificial Intelligence inference, data center, video encoding, and general compute workloads. While AMD EPYC generally remains the player to beat in the enterprise CPU space, Emerald Rapids marks a significant improvement from Intel's side of that battlefield, especially as it pertains to Artificial Intelligence workloads and multi-core performance in general."

Intel's SDE 9.33.0 update confirms 320 MB of L3 cache for "Emerald Rapids," but the next line down provides a major "Granite Rapids" insight—480 MB of L3 cache, representing a 2.8x leap over the previous generation. Team Blue's 6th Gen (all P-core) Xeon processor series is expected to launch within the latter half of 2024. The American multinational technology company is evidently keen to take on AMD in the enterprise CPU market segment, although Team Red is already well ahead with its current crop of L3 cache designations. EPYC CPUs in Genoa and Genoa-X guises offer maximum totals of 384 MB and 1152 MB (respectively). Intel's recently launched "Emerald Rapids" server chips are observed as being a good match against Team Red EPYC "Bergamo" options.

Intel's advanced packaging prowess demonstration took place this week—attendees were able to get an early-ish look at Team Blue's sixth Generation Xeon Scalable "Sapphire Rapids" processors. This multi-tile datacenter-oriented CPU family is projected to hit the market within the first half of 2024, but reports suggest that key enterprise clients have recently received evaluation samples. Coincidentally, renowned hardware leaker—Yuuki_AnS—has managed to source more information from industry insiders. This follows their complete blowout of more mainstream Raptor Lake Refresh desktop SKUs.

The leaked slide presents a bunch of evaluation sample "Granite Rapids-SP" XCC and "Sierra Forest" HCC SKUs. Intel has not officially published core counts for these upcoming "Avenue City" platform product lines. According to their official marketing blurb: "Intel Xeon processors with P-cores (Granite Rapids) are optimized to deliver the lowest total cost of ownership (TCO) for high-core performance-sensitive workloads and general-purpose compute workloads. Today, Xeon enables better AI performance than any other CPU, and Granite Rapids will further enhance AI performance. Built-in accelerators give an additional boost to targeted workloads for even greater performance and efficiency."

At this year's Hot Chips event, Intel provided the first in-depth look at its next-generation Intel Xeon product lineup, built on a new, innovative platform architecture. The platform marks an important evolution for Intel Xeon by introducing processors with a new Efficient-core (E-core) architecture alongside its well-established Performance-core (P-core) architecture. Code-named Sierra Forest and Granite Rapids, respectively, these new products will bring simplicity and flexibility to customers, offering a compatible hardware architecture and shared software stack to tackle critical workloads such as artificial intelligence.

"It is an exciting time for Intel and its Xeon roadmap. We recently shipped our millionth 4th Gen Xeon, our 5th Gen Xeon (code-named Emerald Rapids) will launch in Q4 2023 and our 2024 portfolio of data center products will prove to be a force in the industry," said Lisa Spelman, Intel corporate vice president and general manager of Xeon Products and Solutions.

Intel has published a preview article covering its new AVX10 ISA (Instruction Set Architecture)—the announcement reveals that both P-Cores & E-Cores (on next-gen processors) will be getting support for AVX-512. Team Blue stated: "Intel AVX10 represents a major shift to supporting a high-performance vector ISA across future Intel processors. It allows the developer to maintain a single code-path that achieves high performance across all Intel platforms with the minimum of overhead checking for feature support. Future development of the Intel AVX10 ISA will continue to provide a rich, flexible, and consistent environment that optimally supports both Server and Client products."

Due to technical issues (E-core related), Intel decided to disable AVX-512 for Alder Lake and Raptor Lake client-oriented CPU lineups. AMD has recently adopted the fairly new instruction set for its Ryzen 7040 mobile series, so it is no wonder that Team Blue is attempting to reintroduce it in the near future—AVX-512 was last seen working properly on Rocket and Tiger Lake chips. AVX10 implementation is expected to debut with Granite Rapids (according to Longhorn), and VideoCardz reckons that Intel will get advanced instructions for Efficiency cores working with its Clearwater Forest CPU architecture.

The "Granite Rapids-D" line of upcoming processors are designed for data-center servers on the edge. These non-socketed processors come in BGA4368 packages. The company is reportedly readying at least two key variants of these chips based on core-counts and memory channels. The "Granite Rapids-D" HCC (high core-count) is an MCM of a "Granite Rapids" LCC (low-core count) compute tile, and a single I/O tile with a 4-channel DDR5 memory interface.

The "Granite Rapids-D" XCC (extreme core-count) has one "Granite Rapids" HCC (high core-count) compute tile, and two I/O tiles that make up the chip's 8-channel DDR5 memory interface. A probable reason for the confusion between LCC, HCC, and XCC terminologies for "Granite Rapids-D" is because the compute tiles are carried over from the main "Granite Rapids-SP" server processors, where they mean different things for the core-counts of mainline servers.

Another next-gen Intel Xeon processor has been leaked by momomo_us via Twitter—the subject of the photograph appears to be a Granite Rapids-SP, alongside a new socket type; LGA 4710. These should not be confused with the recent appearance of a Granite Rapids-AP CPU plus LGA 7529 socket. The latest photo showcases two Intel CPUs with new integrated heat spreader (IHS) designs, both housed in carrier frames labeled "LGA 4710-2." The unit on the left seems to be similar in appearance to current-gen Sapphire Rapids-SP units, but the Xeon sitting on the right is getting most of the attention.

YuuKi_AnS (the leaker of last week's larger GNR-AP) pointed out that the smaller socket type is for a platform codenamed "Beechnut City," that is alleged to support Xeon GNR-SP CPUs. They provided a presentation slide of Intel's Beechnut City Main Validation Vehicle (MVV)—this mainboard appears to sport a dual-socket (2S) setup that can house Granite Rapids-SP Xeon CPUs (compatible with the LGA 4710-2 standard) with a maximum 350 W TDP. The spec sheet indicates that the board can support 8-channel DDR5 memory across 32 DIMM slots (DDR5-6400 1DPC / DDR5-5200 2DPC), as well as 88 PCIe Gen 5.0 lanes. The sixth generation Granite Rapids-SP & AP CPUs (based on "Intel 3" process node) are expected to launch in 2H 2024—following the Sierra Forest lineup.

Intel's Birch Stream-AP socket will provide an LGA7529 socket with as many as 7529 pins to power the next generation of CPUs. Today, thanks to Yuuki_Ans on Twitter, we have another set of pictures that highlight the massive scale that these processors offer. We got similar pictures in the past; however, these are more representative of how big the next-generation Xeon processors are. In 2024, Intel plans to split its Xeon lineup into E-core and P-core powered models. However, both CPUs will utilize the same platform to reduce the overall ecosystem's complexity. Thanks to the new pictures, we can see the processor with its heatsink present, with labeling indicating an engineering sample based on little info printed on the metal surface.

Below are the pictures of the Granite Rapids-AP and the LGA7529 socket, along with the specification table. The third image shows current generation Xeon Platinum processor in the LGA7529 socket.

AMD and JEDEC are collaborating to create a new industry standard for DDR5 memory called MRDIMMs (multi-ranked buffered DIMMs). The constant need for bandwidth in server systems provides trouble that can not easily be solved. Adding more memory is difficult, as motherboards can only get so big. Incorporating on-package memory solutions like HBM is expensive and can only scale to a specific memory capacity. However, engineers of JEDEC, with the help of AMD, have come to make a new standard that will try and solve this challenge using the new MRDIMM technology. The concept of MRDIMM is, on paper, straightforward. It combines two DDR5 DIMMs on a single module to effectively double the bandwidth. Specifically, if you take two DDR5 DIMMs running at 4,400 MT/s and connect them to create a single DIMM, you get 8,800 MT/s speeds on a single module. To efficiently use it, a special data mux or buffer will effectively take two Double Data Rate (DDR) DIMMs and convert them into Quad Data Rate (QDR) DIMMs.

The design also allows simultaneous access to both ranks of memory, thanks to the added mux. First-generation MRDIMMs can produce speeds of up to 8,800 MT/s, while the second and third generations modules can go to 12,800 MT/s and 17,600 MT/s, respectively. We expect third-generation MRDIMMs after 2030, so the project is still far away. Additionally, Intel has a similar solution called Multiplexer Combined Ranks DIMM (MCRDIMM) which uses a similar approach. However, Intel's technology is expected to see the light of the day as early as 2024/2025 and beyond the generation of servers, with Granite Rapids likely representing a contender for this technology. SK Hynix already makes MCRDIMMs, and you can see the demonstration of the approach below.

All eyes - especially investors' eyes - are on Intel's data center business today. Intel's Sandra Rivera, Greg Lavender and Lisa Spelman hosted a webinar focused on the company's Data Center and Artificial Intelligence business unit. They offered a big update on Intel's latest market forecasts, hardware plans and the way Intel is empowering developers with software.

Executives dished out updates on Intel's data center business for investors. This included disclosures about future generations of Intel Xeon chips, progress updates on 4th Gen Intel Xeon Scalable processors (code-named Sapphire Rapids) and demos of Intel hardware tackling the competition, heavy AI workloads and more.

Xeon Roadmap Roll Call
Among Sapphire Rapids, Emerald Rapids, Sierra Forest and Granite Rapids, there is a lot going on in the server CPU business. Here's your Xeon roadmap updates in order of appearance:

A set of detailed photos has been uploaded to a blog on the Chinese Bilibili site, and the subject matter is an engineering sample of a motherboard that features Intel's next generation LGA 7529 socket. Specifications and photos relating to this platform have cropped up in the past, but the latest leak offers many new tidbits of information. The Bilibili blogger placed a Sapphire Rapids Xeon Processor on top of the the new socket, and this provides an interesting point of reference - it demonstrates the expansive physical footprint that the fifth-generation platform occupies on the board.

This year's Sapphire Rapids LGA 4677 (Socket E) is already considered to be a sizeable prospect - measuring at 61 × 82 mm. The upcoming Mountain Stream platform (LGA 7529) is absolutely huge in comparison, with eyeball estimates placing it possessing rough dimensions (including the retention arm) of 66 × 92.5 mm. The fifth generation platform is designed to run Intel's Granite Rapids and Sierra Forest CPUs - this family of Xeons featuring scalable microarchitecture is expected to launch in 2024. The code name "Avenue City" has been given to a reference platform that features a dual socket configuration.

Today, thanks to Yuuki_Ans on the Chinese Bilibili forum, we have more information about the upcoming "Avenue City" platform that powers Granite Rapids and Sierra Forest. Intel's forthcoming Granite Rapids and Sierra Forest Xeon processors will diverge the Xeon family into two offerings: one optimized for performance/core equipped with P-cores and the other for power/core equipped with E-cores. The reference platform Intel designs and shares with OEMs internally is a 16.7" x 20" board with 20 PCB layers, made as a dual-socket solution. Featuring two massive LGA-7529 sockets, the reference design shows the basic layout for a server powered by these new Xeons.

Capable of powering Granite Rapids / Sierra Forest-AP processors of up to 500 Watts, the platform also accommodates next-generation I/O. Featuring 24 DDR5 DIMMs with support for 12-channel memory, with memory speeds of up to 6400 MT/s. The PCIe selection includes six PCIe Gen 5 x16 links supporting CXL cache coherent protocol and 6x24 UPI links. Additionally, we have another piece of information that Granite Rapids will come with up to 128 cores and 256 threads in both regular and HBM-powered Xeon Max flavoring. You can see storage and reference platform configuration details on the slides below.

Intel's upcoming LGA-7529 socket designed for next-generation Xeon processors has been pictured, thanks to Yuuki_Ans and Hassan Mujtaba. According to the latest photos, we see the massive LGA-7529 socket with an astonishing 7,529 pins placed inside of a single socket. Made for Intel's upcoming "Birch Stream" platform, this socket is going to power Intel's next-generation "Sierra Forest" Xeon processors. With Sierra Forest representing a new way of thinking about Xeon processors, it also requires a special socket. Built on Intel 3 manufacturing process, these Xeon processors use only E-cores in their design to respond to AMD EPYC Bergamo with Zen4c.

The Intel Xeon roadmap will split in 2024, where Sierra Forest will populate dense and efficient cloud computing with E-cores, while its Granite Rapids sibling will power high-performance computing using P-cores. This interesting split will be followed by the new LGA-7529 socket pictured below, which is a step up from Intel's current LGA-4677 socket with 4677 pins used for Sapphire Rapids. With higher core densities and performance targets, the additional pins are likely to be mostly power/ground pins, while the smaller portion is picking up the additional I/O of the processor.20:20 UTC: Updated with motherboard picture of dual-socket LGA-7529 system, thanks to findings of @9550pro lurking in the Chinese forums.

Intel's server processor lineup led by the 4th Gen Xeon Scalable "Sapphire Rapids" processors face stiff competition from AMD 4th Gen EPYC "Genoa" processors that offer significantly higher multi-threaded performance per Watt on account of a higher CPU core-count. The gap is only set to widen, as AMD prepares to launch the "Bergamo" processor for cloud data-centers, with core-counts of up to 128-core/256-thread per socket. A technologically-embattled Intel is preparing quick counters as many as three new server microarchitecture launches over the next 23 months, according to Intel, in its Q4-2022 Financial Results presentation.

The 4th Gen Xeon Scalable "Sapphire Rapids," with a core-count of up to 60-core/120-thread, and various application-specific accelerators, witnessed a quiet launch earlier this month, and is shipping to Intel customers. The company says that it will be joined by the Xeon Scalable "Emerald Rapids" architecture in the second half of 2023; followed by "Granite Rapids" and "Sierra Forest" in 2024. Built on the same LGA4677 package as "Sapphire Rapids," the new "Emerald Rapids" MCM packs up to 64 "Raptor Cove" CPU cores, which support higher clock-speeds, higher memory speeds, and introduce the new Intel Trust Domain Extensions (TDX) instruction-set. The processor retains the 8-channel DDR5 memory interface, but with higher native memory speeds. The chip's main serial interface is a PCI-Express Gen 5 root-complex with 80 lanes. The processor will be built on the last foundry-level refinement of the Intel 7 node (10 nm Enhanced SuperFin); many of these refinements were introduced with the company's 13th Gen Core "Raptor Lake" client processors.